[dpdk-dev] [PATCH v4 8/8] net/mlx4: mitigate Tx path memory barriers

Adrien Mazarguil adrien.mazarguil at 6wind.com
Thu Nov 2 14:43:24 CET 2017


On Tue, Oct 31, 2017 at 06:21:33PM +0000, Matan Azrad wrote:
> Replace most of the memory barriers by IO memory barriers since they
> are all targeted to the DRAM; This improves code efficiency for
> systems which force store order between different addresses.
> 
> Only the doorbell register store should be protected by memory barrier
> since it is targeted to the PCI memory domain.
> 
> Limit pre byte count store IO memory barrier for systems with cache
> line size smaller than 64B (TXBB size).
> 
> This patch improves Tx performance by 0.2MPPS for one segment 64B
> packets via 1 queue with 1 core test.
> 
> Signed-off-by: Matan Azrad <matan at mellanox.com>

Acked-by: Adrien Mazarguil <adrien.mazarguil at 6wind.com>

-- 
Adrien Mazarguil
6WIND


More information about the dev mailing list