[dpdk-dev] [PATCH v3 03/32] crypto/octeontx: add register addresses

Anoob Joseph anoob.joseph at caviumnetworks.com
Fri Oct 5 14:58:54 CEST 2018


From: Ankur Dwivedi <ankur.dwivedi at caviumnetworks.com>

Signed-off-by: Ankur Dwivedi <ankur.dwivedi at caviumnetworks.com>
Signed-off-by: Anoob Joseph <anoob.joseph at caviumnetworks.com>
Signed-off-by: Murthy NSSR <nidadavolu.murthy at caviumnetworks.com>
Signed-off-by: Nithin Dabilpuram <nithin.dabilpuram at caviumnetworks.com>
Signed-off-by: Ragothaman Jayaraman <rjayaraman at caviumnetworks.com>
Signed-off-by: Srisivasubramanian S <ssrinivasan at caviumnetworks.com>
Signed-off-by: Tejasree Kondoj <kondoj.tejasree at caviumnetworks.com>
---
 drivers/crypto/octeontx/otx_cryptodev_hw_access.h | 47 +++++++++++++++++++++++
 1 file changed, 47 insertions(+)
 create mode 100644 drivers/crypto/octeontx/otx_cryptodev_hw_access.h

diff --git a/drivers/crypto/octeontx/otx_cryptodev_hw_access.h b/drivers/crypto/octeontx/otx_cryptodev_hw_access.h
new file mode 100644
index 0000000..288ee41
--- /dev/null
+++ b/drivers/crypto/octeontx/otx_cryptodev_hw_access.h
@@ -0,0 +1,47 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2018 Cavium, Inc
+ */
+
+#ifndef _OTX_CRYPTODEV_HW_ACCESS_H_
+#define _OTX_CRYPTODEV_HW_ACCESS_H_
+
+/*
+ * CPT Registers map for 81xx
+ */
+
+/* VF registers */
+#define CPTX_VQX_CTL(a, b)		(0x0000100ll + 0x1000000000ll * \
+					 ((a) & 0x0) + 0x100000ll * (b))
+#define CPTX_VQX_SADDR(a, b)		(0x0000200ll + 0x1000000000ll * \
+					 ((a) & 0x0) + 0x100000ll * (b))
+#define CPTX_VQX_DONE_WAIT(a, b)	(0x0000400ll + 0x1000000000ll * \
+					 ((a) & 0x0) + 0x100000ll * (b))
+#define CPTX_VQX_INPROG(a, b)		(0x0000410ll + 0x1000000000ll * \
+					 ((a) & 0x0) + 0x100000ll * (b))
+#define CPTX_VQX_DONE(a, b)		(0x0000420ll + 0x1000000000ll * \
+					 ((a) & 0x1) + 0x100000ll * (b))
+#define CPTX_VQX_DONE_ACK(a, b)		(0x0000440ll + 0x1000000000ll * \
+					 ((a) & 0x1) + 0x100000ll * (b))
+#define CPTX_VQX_DONE_INT_W1S(a, b)	(0x0000460ll + 0x1000000000ll * \
+					 ((a) & 0x1) + 0x100000ll * (b))
+#define CPTX_VQX_DONE_INT_W1C(a, b)	(0x0000468ll + 0x1000000000ll * \
+					 ((a) & 0x1) + 0x100000ll * (b))
+#define CPTX_VQX_DONE_ENA_W1S(a, b)	(0x0000470ll + 0x1000000000ll * \
+					 ((a) & 0x1) + 0x100000ll * (b))
+#define CPTX_VQX_DONE_ENA_W1C(a, b)	(0x0000478ll + 0x1000000000ll * \
+					 ((a) & 0x1) + 0x100000ll * (b))
+#define CPTX_VQX_MISC_INT(a, b)		(0x0000500ll + 0x1000000000ll * \
+					 ((a) & 0x1) + 0x100000ll * (b))
+#define CPTX_VQX_MISC_INT_W1S(a, b)	(0x0000508ll + 0x1000000000ll * \
+					 ((a) & 0x1) + 0x100000ll * (b))
+#define CPTX_VQX_MISC_ENA_W1S(a, b)	(0x0000510ll + 0x1000000000ll * \
+					 ((a) & 0x1) + 0x100000ll * (b))
+#define CPTX_VQX_MISC_ENA_W1C(a, b)	(0x0000518ll + 0x1000000000ll * \
+					 ((a) & 0x1) + 0x100000ll * (b))
+#define CPTX_VQX_DOORBELL(a, b)		(0x0000600ll + 0x1000000000ll * \
+					 ((a) & 0x1) + 0x100000ll * (b))
+#define CPTX_VFX_PF_MBOXX(a, b, c)	(0x0001000ll + 0x1000000000ll * \
+					 ((a) & 0x1) + 0x100000ll * (b) + \
+					 8ll * ((c) & 0x1))
+
+#endif /* _OTX_CRYPTODEV_HW_ACCESS_H_ */
-- 
2.7.4



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