[dpdk-dev] [PATCH 04/10] crypto/caam_jr: add device configuration routines
Akhil Goyal
akhil.goyal at nxp.com
Tue Sep 18 15:59:49 CEST 2018
Hi Gagan,
On 9/13/2018 11:38 AM, Gagandeep Singh wrote:
> From: Hemant Agrawal <hemant.agrawal at nxp.com>
>
> Signed-off-by: Gagandeep Singh <g.singh at nxp.com>
> Signed-off-by: Hemant Agrawal <hemant.agrawal at nxp.com>
> ---
> drivers/crypto/caam_jr/caam_jr.c | 100 +++++++++++-
> drivers/crypto/caam_jr/caam_jr.h | 257 +++++++++++++++++++++++++++++++
> 2 files changed, 356 insertions(+), 1 deletion(-)
> create mode 100644 drivers/crypto/caam_jr/caam_jr.h
>
> diff --git a/drivers/crypto/caam_jr/caam_jr.c b/drivers/crypto/caam_jr/caam_jr.c
> index 9d5f5b79b..43fe5233b 100644
> --- a/drivers/crypto/caam_jr/caam_jr.c
> +++ b/drivers/crypto/caam_jr/caam_jr.c
> @@ -22,6 +22,7 @@
> #include <hw/desc/common.h>
> #include <of.h>
> #include <caam_jr_hw_specific.h>
> +#include <caam_jr.h>
> #include <caam_jr_pvt.h>
> #include <caam_jr_log.h>
>
> @@ -104,6 +105,90 @@ static void hw_flush_job_ring(struct sec_job_ring_t *job_ring,
> }
>
>
> +static int
> +caam_jr_dev_configure(struct rte_cryptodev *dev,
> + struct rte_cryptodev_config *config __rte_unused)
> +{
> + char str[20];
> + struct sec_job_ring_t *internals;
> +
> + PMD_INIT_FUNC_TRACE();
> +
> + internals = dev->data->dev_private;
> + sprintf(str, "ctx_pool_%d", dev->data->dev_id);
> + if (!internals->ctx_pool) {
> + internals->ctx_pool = rte_mempool_create((const char *)str,
> + CTX_POOL_NUM_BUFS,
> + sizeof(struct caam_jr_op_ctx),
> + CTX_POOL_CACHE_SIZE, 0,
> + NULL, NULL, NULL, NULL,
> + SOCKET_ID_ANY, 0);
> + if (!internals->ctx_pool) {
> + CAAM_JR_ERR("%s create failed\n", str);
> + return -ENOMEM;
> + }
> + } else
> + CAAM_JR_INFO("mempool already created for dev_id : %d",
> + dev->data->dev_id);
> +
> + return 0;
> +}
> +
> +static int
> +caam_jr_dev_start(struct rte_cryptodev *dev __rte_unused)
> +{
> + PMD_INIT_FUNC_TRACE();
> + return 0;
> +}
> +
> +static void
> +caam_jr_dev_stop(struct rte_cryptodev *dev __rte_unused)
> +{
> + PMD_INIT_FUNC_TRACE();
> +}
> +
> +static int
> +caam_jr_dev_close(struct rte_cryptodev *dev)
> +{
> + struct sec_job_ring_t *internals;
> +
> + PMD_INIT_FUNC_TRACE();
> +
> + if (dev == NULL)
> + return -ENOMEM;
> +
> + internals = dev->data->dev_private;
> + rte_mempool_free(internals->ctx_pool);
> + internals->ctx_pool = NULL;
> +
> + return 0;
> +}
> +
> +static void
> +caam_jr_dev_infos_get(struct rte_cryptodev *dev,
> + struct rte_cryptodev_info *info)
> +{
> + struct sec_job_ring_t *internals = dev->data->dev_private;
> +
> + PMD_INIT_FUNC_TRACE();
> + if (info != NULL) {
> + info->max_nb_queue_pairs = internals->max_nb_queue_pairs;
> + info->feature_flags = dev->feature_flags;
> + info->capabilities = caam_jr_capabilities;
> + info->sym.max_nb_sessions = internals->max_nb_sessions;
> + info->driver_id = cryptodev_driver_id;
> + }
> +}
> +
> +static struct rte_cryptodev_ops caam_jr_ops = {
> + .dev_configure = caam_jr_dev_configure,
> + .dev_start = caam_jr_dev_start,
> + .dev_stop = caam_jr_dev_stop,
> + .dev_close = caam_jr_dev_close,
> + .dev_infos_get = caam_jr_dev_infos_get,
> +};
> +
> +
> /* @brief Flush job rings of any processed descs.
> * The processed descs are silently dropped,
> * WITHOUT being notified to UA.
> @@ -366,7 +451,20 @@ caam_jr_dev_init(const char *name,
> }
>
> dev->driver_id = cryptodev_driver_id;
> - dev->dev_ops = NULL;
> + dev->dev_ops = &caam_jr_ops;
> +
> + /* register rx/tx burst functions for data path */
> + dev->dequeue_burst = NULL;
> + dev->enqueue_burst = NULL;
> + dev->feature_flags = RTE_CRYPTODEV_FF_SYMMETRIC_CRYPTO |
> + RTE_CRYPTODEV_FF_HW_ACCELERATED |
> + RTE_CRYPTODEV_FF_SYM_OPERATION_CHAINING |
> + RTE_CRYPTODEV_FF_SECURITY |
> + RTE_CRYPTODEV_FF_IN_PLACE_SGL |
> + RTE_CRYPTODEV_FF_OOP_SGL_IN_SGL_OUT |
> + RTE_CRYPTODEV_FF_OOP_SGL_IN_LB_OUT |
> + RTE_CRYPTODEV_FF_OOP_LB_IN_SGL_OUT |
> + RTE_CRYPTODEV_FF_OOP_LB_IN_LB_OUT;
>
> /* For secondary processes, we don't initialise any further as primary
> * has already done this work. Only check we don't need a different
> diff --git a/drivers/crypto/caam_jr/caam_jr.h b/drivers/crypto/caam_jr/caam_jr.h
> new file mode 100644
> index 000000000..d7c36ca9d
> --- /dev/null
> +++ b/drivers/crypto/caam_jr/caam_jr.h
> @@ -0,0 +1,257 @@
> +/* SPDX-License-Identifier: BSD-3-Clause
> + * Copyright 2017-2018 NXP
> + */
> +
> +#ifndef CAAM_JR_H
> +#define CAAM_JR_H
> +
> +static const struct rte_cryptodev_capabilities caam_jr_capabilities[] = {
> + { /* MD5 HMAC */
> + .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
> + {.sym = {
> + .xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
> + {.auth = {
> + .algo = RTE_CRYPTO_AUTH_MD5_HMAC,
> + .block_size = 64,
> + .key_size = {
> + .min = 1,
> + .max = 64,
> + .increment = 1
> + },
> + .digest_size = {
> + .min = 1,
> + .max = 16,
> + .increment = 1
> + },
> + .iv_size = { 0 }
> + }, }
> + }, }
> + },
> + { /* SHA1 HMAC */
> + .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
> + {.sym = {
> + .xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
> + {.auth = {
> + .algo = RTE_CRYPTO_AUTH_SHA1_HMAC,
> + .block_size = 64,
> + .key_size = {
> + .min = 1,
> + .max = 64,
> + .increment = 1
> + },
> + .digest_size = {
> + .min = 1,
> + .max = 20,
> + .increment = 1
> + },
> + .iv_size = { 0 }
> + }, }
> + }, }
> + },
> + { /* SHA224 HMAC */
> + .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
> + {.sym = {
> + .xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
> + {.auth = {
> + .algo = RTE_CRYPTO_AUTH_SHA224_HMAC,
> + .block_size = 64,
> + .key_size = {
> + .min = 1,
> + .max = 64,
> + .increment = 1
> + },
> + .digest_size = {
> + .min = 1,
> + .max = 28,
> + .increment = 1
> + },
> + .iv_size = { 0 }
> + }, }
> + }, }
> + },
> + { /* SHA256 HMAC */
> + .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
> + {.sym = {
> + .xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
> + {.auth = {
> + .algo = RTE_CRYPTO_AUTH_SHA256_HMAC,
> + .block_size = 64,
> + .key_size = {
> + .min = 1,
> + .max = 64,
> + .increment = 1
> + },
> + .digest_size = {
> + .min = 1,
> + .max = 32,
> + .increment = 1
> + },
> + .iv_size = { 0 }
> + }, }
> + }, }
> + },
> + { /* SHA384 HMAC */
> + .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
> + {.sym = {
> + .xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
> + {.auth = {
> + .algo = RTE_CRYPTO_AUTH_SHA384_HMAC,
> + .block_size = 128,
> + .key_size = {
> + .min = 1,
> + .max = 128,
> + .increment = 1
> + },
> + .digest_size = {
> + .min = 1,
> + .max = 48,
> + .increment = 1
> + },
> + .iv_size = { 0 }
> + }, }
> + }, }
> + },
> + { /* SHA512 HMAC */
> + .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
> + {.sym = {
> + .xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
> + {.auth = {
> + .algo = RTE_CRYPTO_AUTH_SHA512_HMAC,
> + .block_size = 128,
> + .key_size = {
> + .min = 1,
> + .max = 128,
> + .increment = 1
> + },
> + .digest_size = {
> + .min = 1,
> + .max = 64,
> + .increment = 1
> + },
> + .iv_size = { 0 }
> + }, }
> + }, }
> + },
> + { /* AES GCM */
> + .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
> + {.sym = {
> + .xform_type = RTE_CRYPTO_SYM_XFORM_AEAD,
> + {.aead = {
> + .algo = RTE_CRYPTO_AEAD_AES_GCM,
> + .block_size = 16,
> + .key_size = {
> + .min = 16,
> + .max = 32,
> + .increment = 8
> + },
> + .digest_size = {
> + .min = 8,
> + .max = 16,
> + .increment = 4
> + },
> + .aad_size = {
> + .min = 0,
> + .max = 240,
> + .increment = 1
> + },
> + .iv_size = {
> + .min = 12,
> + .max = 12,
> + .increment = 0
> + },
> + }, }
> + }, }
> + },
> + { /* AES CBC */
> + .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
> + {.sym = {
> + .xform_type = RTE_CRYPTO_SYM_XFORM_CIPHER,
> + {.cipher = {
> + .algo = RTE_CRYPTO_CIPHER_AES_CBC,
> + .block_size = 16,
> + .key_size = {
> + .min = 16,
> + .max = 32,
> + .increment = 8
> + },
> + .iv_size = {
> + .min = 16,
> + .max = 16,
> + .increment = 0
> + }
> + }, }
> + }, }
> + },
> + { /* AES CTR */
> + .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
> + {.sym = {
> + .xform_type = RTE_CRYPTO_SYM_XFORM_CIPHER,
> + {.cipher = {
> + .algo = RTE_CRYPTO_CIPHER_AES_CTR,
> + .block_size = 16,
> + .key_size = {
> + .min = 16,
> + .max = 32,
> + .increment = 8
> + },
> + .iv_size = {
> + .min = 16,
> + .max = 16,
> + .increment = 0
> + }
> + }, }
> + }, }
> + },
> + { /* 3DES CBC */
> + .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
> + {.sym = {
> + .xform_type = RTE_CRYPTO_SYM_XFORM_CIPHER,
> + {.cipher = {
> + .algo = RTE_CRYPTO_CIPHER_3DES_CBC,
> + .block_size = 8,
> + .key_size = {
> + .min = 16,
> + .max = 24,
> + .increment = 8
> + },
> + .iv_size = {
> + .min = 8,
> + .max = 8,
> + .increment = 0
> + }
> + }, }
> + }, }
> + },
> +
> + RTE_CRYPTODEV_END_OF_CAPABILITIES_LIST()
> +};
capabilities shall be added in your 08/10.
> +
> +static const struct rte_security_capability caam_jr_security_cap[] = {
> + { /* IPsec Lookaside Protocol offload ESP Transport Egress */
> + .action = RTE_SECURITY_ACTION_TYPE_LOOKASIDE_PROTOCOL,
> + .protocol = RTE_SECURITY_PROTOCOL_IPSEC,
> + .ipsec = {
> + .proto = RTE_SECURITY_IPSEC_SA_PROTO_ESP,
> + .mode = RTE_SECURITY_IPSEC_SA_MODE_TUNNEL,
> + .direction = RTE_SECURITY_IPSEC_SA_DIR_EGRESS,
> + .options = { 0 }
> + },
> + .crypto_capabilities = caam_jr_capabilities
> + },
> + { /* IPsec Lookaside Protocol offload ESP Tunnel Ingress */
> + .action = RTE_SECURITY_ACTION_TYPE_LOOKASIDE_PROTOCOL,
> + .protocol = RTE_SECURITY_PROTOCOL_IPSEC,
> + .ipsec = {
> + .proto = RTE_SECURITY_IPSEC_SA_PROTO_ESP,
> + .mode = RTE_SECURITY_IPSEC_SA_MODE_TUNNEL,
> + .direction = RTE_SECURITY_IPSEC_SA_DIR_INGRESS,
> + .options = { 0 }
> + },
> + .crypto_capabilities = caam_jr_capabilities
> + },
> + {
> + .action = RTE_SECURITY_ACTION_TYPE_NONE
> + }
> +};
> +
security capabilities shall be added in your 10/10 patch.
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