[dpdk-dev] [EXT] Re: [PATCH v2 2/4] meson: change default cache line size for armv8

[Yongseok Koh]

> On Apr 18, 2019, at 1:23 AM, Hemant Agrawal <hemant.agrawal at nxp.com> wrote:
> 
>> -----Original Message-----
>> From: dev <dev-bounces at dpdk.org> On Behalf Of Honnappa Nagarahalli
>> Sent: Thursday, April 18, 2019 10:31 AM
>> To: yskoh at mellanox.com; bruce.richardson at intel.com; jerinj at marvell.com;
>> pbhagavatula at marvell.com; shahafs at mellanox.com
>> Cc: dev at dpdk.org; thomas at monjalon.net; Gavin Hu (Arm Technology
>> China) <Gavin.Hu at arm.com>; Honnappa Nagarahalli
>> <Honnappa.Nagarahalli at arm.com>; nd <nd at arm.com>; nd <nd at arm.com>
>> Subject: [EXT] Re: [dpdk-dev] [PATCH v2 2/4] meson: change default cache
>> line size for armv8
>> 
> 
>>> 
>>> Currently, the cache line size of armv8 CPUs having Implementor ID of
>>> 0x41 is
>>> 64 bytes.
>> I guess you meant to say 128 bytes
> 
> 
> "the current default is 128, changing it to 64."

Yep, the message was wrong. Will fix it.

>>> Signed-off-by: Yongseok Koh <yskoh at mellanox.com>
>>> ---
>>> 
>>> v2:
>>> * introduce flags_arm replacing flags_generic instead of using the
>>> extra flags
>>> 
>>> config/arm/meson.build | 7 ++++++-
>>> 1 file changed, 6 insertions(+), 1 deletion(-)
>>> 
>>> diff --git a/config/arm/meson.build b/config/arm/meson.build index
>>> 22a062bad9..1db4ad2ee7 100644
>>> --- a/config/arm/meson.build
>>> +++ b/config/arm/meson.build
>>> @@ -32,6 +32,11 @@ flags_generic = [
>>>      ['RTE_MAX_LCORE', 256],
>>>      ['RTE_USE_C11_MEM_MODEL', true],
>>>      ['RTE_CACHE_LINE_SIZE', 128]]
>>> +flags_arm = [
>>> +     ['RTE_MACHINE', '"armv8a"'],
>>> +     ['RTE_MAX_LCORE', 256],
>> I am not aware of any implementations with implementor ID 0x41. Bluefield
>> is the first one I am aware of. May be we can keep this smaller, 16?
> 
> NXP also support implementer as 0x41, 16 will be good. 

BlueField has 16 cores so yes, it is good.

Thanks,
Yongseok

> 
>> 
>>> +     ['RTE_USE_C11_MEM_MODEL', true],
>>> +     ['RTE_CACHE_LINE_SIZE', 64]]
>>> flags_cavium = [
>>>      ['RTE_CACHE_LINE_SIZE', 128],
>>>      ['RTE_MAX_NUMA_NODES', 2],
>>> @@ -88,7 +93,7 @@ machine_args_cavium = [
>>> 
>>> ## Arm implementer ID (ARM DDI 0487C.a, Section G7.2.106, Page
>>> G7-5321) impl_generic = ['Generic armv8', flags_generic,
>>> machine_args_generic]
>>> -impl_0x41 = ['Arm', flags_generic, machine_args_generic]
>>> +impl_0x41 = ['Arm', flags_arm, machine_args_generic]
>>> impl_0x42 = ['Broadcom', flags_generic, machine_args_generic]
>>> impl_0x43 = ['Cavium', flags_cavium, machine_args_cavium]
>>> impl_0x44 = ['DEC', flags_generic, machine_args_generic]
>>> --
>>> 2.11.0