[dpdk-dev] [EXT] Default cacheline size for ARM

[Honnappa Nagarahalli]

> 
> On Fri, 2019-01-04 at 19:59 +0000, Yongseok Koh wrote:
> > -------------------------------------------------------------------
> > ---
> > Hi,
> >
> > The cacheline size (RTE_CACHE_LINE_SIZE) for ARM CPUs is set to be
> > 128B by default. Mellanox's BlueField is an ARM CPU having Cortex-A72
> > and its CL size is 64B.
Just wondering how many devices are out there with 128B cache line? I also have not heard about any future devices with 128B cache line. If the majority is 64B, why not keep 64B as the default?

> >
> > I can add config/defconfig_arm64-bluefield-linuxapp-gcc for legacy
> > build anyway.
> >
> 
> Makes sense.
> 
> > For the meson build, I know it parses the Main ID register to figure
> > out Implementor ID and Part Number. However, Mellanox doesn't program
> > our own ID yet but we set the Part Number as 0xd08 (A72).
> > According to my folks, ARM's A53, A57, A72, and A73 designs all have
> > 64B CL. If that's true, can I push a patch to make the change?
> 
> Yes. Broadcom Stingray has the same situation i.e Use flags_generic,
> machine_args_generic
> 
This will solve only the native compilation issue. It will not address distro compilation (may be this is not your goal?).

> >
> > Please comment.
> >
> >
> > Thanks,
> > Yongseok
> >