[dpdk-dev] [PATCH 11/44] event/octeontx2: add SSO GWS and GGRP IRQ handlers

Jerin Jacob Kollanukkaran jerinj at marvell.com
Mon Jun 17 10:04:16 CEST 2019


> -----Original Message-----
> From: pbhagavatula at marvell.com <pbhagavatula at marvell.com>
> Sent: Sunday, June 2, 2019 12:23 AM
> To: Jerin Jacob Kollanukkaran <jerinj at marvell.com>; Pavan Nikhilesh
> Bhagavatula <pbhagavatula at marvell.com>
> Cc: dev at dpdk.org
> Subject: [dpdk-dev] [PATCH 11/44] event/octeontx2: add SSO GWS and GGRP
> IRQ handlers
> 
> From: Pavan Nikhilesh <pbhagavatula at marvell.com>
> 
> Register and implement SSO GWS and GGRP IRQ handlers for error interrupts.
> 
> Signed-off-by: Pavan Nikhilesh <pbhagavatula at marvell.com>
> Signed-off-by: Jerin Jacob <jerinj at marvell.com>
> ---
> +#include "otx2_evdev.h"
> +
> +static void
> +sso_lf_irq(void *param)
> +{
> +	uintptr_t base = (uintptr_t)param;
> +	uint64_t intr;
> +	uint8_t ggrp;
> +
> +	ggrp = (base >> 12) & 0xFF;
> +
> +	intr = otx2_read64(base + SSO_LF_GGRP_INT);
> +	if (intr == 0)
> +		return;
> +
> +	otx2_err("GGRP %d GGRP_INT=0x%" PRIx64 "", ggrp, intr);
> +
> +	/* Clear interrupt */
> +	otx2_write64(intr, base + SSO_LF_GGRP_INT);
> +
> +	abort();


Remove abort() from driver.

> +}
> +
> +static int
> +sso_lf_register_irq(const struct rte_eventdev *event_dev, uint16_t
> ggrp_msixoff,
> +		    uintptr_t base)
> +{
> +	struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(event_dev->dev);
> +	struct rte_intr_handle *handle = &pci_dev->intr_handle;
> +	int rc, vec;
> +
> +	vec = ggrp_msixoff + SSO_LF_INT_VEC_GRP;
> +
> +	/* Clear err interrupt */
> +	otx2_write64(~0ull, base + SSO_LF_GGRP_INT_ENA_W1C);
> +	/* Set used interrupt vectors */
> +	rc = otx2_register_irq(handle, sso_lf_irq, (void *)base, vec);
> +	/* Enable hw interrupt */
> +	otx2_write64(~0ull, base + SSO_LF_GGRP_INT_ENA_W1S);
> +
> +	return rc;
> +}
> +
> +static void
> +ssow_lf_irq(void *param)
> +{
> +	uintptr_t base = (uintptr_t)param;
> +	uint8_t gws = (base >> 12) & 0xFF;
> +	uint64_t intr;
> +
> +	intr = otx2_read64(base + SSOW_LF_GWS_INT);
> +	if (intr == 0)
> +		return;
> +
> +	otx2_err("GWS %d GWS_INT=0x%" PRIx64 "", gws, intr);
> +
> +	/* Clear interrupt */
> +	otx2_write64(intr, base + SSOW_LF_GWS_INT);
> +
> +	abort();

Remove abort() from driver.





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