[dpdk-dev] [PATCH 32/44] event/octeontx2: add devargs to modify chunk slots

[Jerin Jacob Kollanukkaran]

> -----Original Message-----
> From: pbhagavatula at marvell.com <pbhagavatula at marvell.com>
> Sent: Sunday, June 2, 2019 12:24 AM
> To: Jerin Jacob Kollanukkaran <jerinj at marvell.com>; Pavan Nikhilesh
> Bhagavatula <pbhagavatula at marvell.com>
> Cc: dev at dpdk.org
> Subject: [dpdk-dev] [PATCH 32/44] event/octeontx2: add devargs to modify
> chunk slots
> 
> From: Pavan Nikhilesh <pbhagavatula at marvell.com>
> 
> Add devargs support to modify number of chunk slots. Chunks are used to store
> event timers, a chunk can be visualised as an array where the last element points
> to the next chunk and rest of them are used to store events. TIM traverses the
> list of chunks and enqueues the event timers to SSO.
> If no argument is passed then a default value of 255 is taken.
> Example:
> 
> 	--dev "0002:0e:00.0,tim_chnk_slots=511"
> 
> Signed-off-by: Pavan Nikhilesh <pbhagavatula at marvell.com>
> ---
>  drivers/event/octeontx2/otx2_tim_evdev.c | 11 ++++++++++-
> drivers/event/octeontx2/otx2_tim_evdev.h |  2 ++
>  2 files changed, 12 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/event/octeontx2/otx2_tim_evdev.c
> b/drivers/event/octeontx2/otx2_tim_evdev.c
> index 9cceafd77..bba6cc609 100644
> --- a/drivers/event/octeontx2/otx2_tim_evdev.c
> +++ b/drivers/event/octeontx2/otx2_tim_evdev.c
> @@ -240,7 +240,7 @@ otx2_tim_ring_create(struct rte_event_timer_adapter
> *adptr)
>  	tim_ring->tck_nsec = RTE_ALIGN_MUL_CEIL(rcfg->timer_tick_ns, 10);
>  	tim_ring->max_tout = rcfg->max_tmo_ns;
>  	tim_ring->nb_bkts = (tim_ring->max_tout / tim_ring->tck_nsec);
> -	tim_ring->chunk_sz = OTX2_TIM_RING_DEF_CHNK_SZ;
> +	tim_ring->chunk_sz = dev->chunk_sz;
>  	nb_timers = rcfg->nb_timers;
>  	tim_ring->disable_npa = dev->disable_npa;
> 
> @@ -355,6 +355,7 @@ otx2_tim_caps_get(const struct rte_eventdev *evdev,
> uint64_t flags,  }
> 
>  #define OTX2_TIM_DISABLE_NPA	"tim_disable_npa"
> +#define OTX2_TIM_CHNK_SLOTS	"tim_chnk_slots"
> 
>  static void
>  tim_parse_devargs(struct rte_devargs *devargs, struct otx2_tim_evdev *dev)
> @@ -370,6 +371,8 @@ tim_parse_devargs(struct rte_devargs *devargs, struct
> otx2_tim_evdev *dev)
> 
>  	rte_kvargs_process(kvlist, OTX2_TIM_DISABLE_NPA,
>  			   &parse_kvargs_flag, &dev->disable_npa);
> +	rte_kvargs_process(kvlist, OTX2_TIM_CHNK_SLOTS,
> +			   &parse_kvargs_value, &dev->chunk_slots);
>  }
> 
>  void
> @@ -423,6 +426,12 @@ otx2_tim_init(struct rte_pci_device *pci_dev, struct
> otx2_dev *cmn_dev)
>  		goto mz_free;
>  	}
> 
> +	if (!dev->chunk_slots)
> +		dev->chunk_sz = OTX2_TIM_RING_DEF_CHNK_SZ;
> +	else
> +		dev->chunk_sz = (dev->chunk_slots + 1) *
> +			OTX2_TIM_CHUNK_ALIGNMENT;

Please check the chuck_sz upper bound also.