[dpdk-dev] [PATCH v3 29/42] event/octeontx2: allow TIM to optimize config

pbhagavatula at marvell.com pbhagavatula at marvell.com
Fri Jun 28 20:23:40 CEST 2019


From: Pavan Nikhilesh <pbhagavatula at marvell.com>

Allow TIM to optimize user supplied configuration based on
RTE_EVENT_TIMER_ADAPTER_F_ADJUST_RES flag.

Signed-off-by: Pavan Nikhilesh <pbhagavatula at marvell.com>
---
 drivers/event/octeontx2/otx2_evdev.h     |  1 +
 drivers/event/octeontx2/otx2_tim_evdev.c | 62 +++++++++++++++++++++++-
 drivers/event/octeontx2/otx2_tim_evdev.h |  3 ++
 3 files changed, 64 insertions(+), 2 deletions(-)

diff --git a/drivers/event/octeontx2/otx2_evdev.h b/drivers/event/octeontx2/otx2_evdev.h
index fc8dde416..1e15b7e1c 100644
--- a/drivers/event/octeontx2/otx2_evdev.h
+++ b/drivers/event/octeontx2/otx2_evdev.h
@@ -76,6 +76,7 @@
 #define NSEC2USEC(__ns)			((__ns) / 1E3)
 #define USEC2NSEC(__us)                 ((__us) * 1E3)
 #define NSEC2TICK(__ns, __freq)		(((__ns) * (__freq)) / 1E9)
+#define TICK2NSEC(__tck, __freq)	(((__tck) * 1E9) / (__freq))
 
 enum otx2_sso_lf_type {
 	SSO_LF_GGRP,
diff --git a/drivers/event/octeontx2/otx2_tim_evdev.c b/drivers/event/octeontx2/otx2_tim_evdev.c
index e24f7ce9e..a0953bb49 100644
--- a/drivers/event/octeontx2/otx2_tim_evdev.c
+++ b/drivers/event/octeontx2/otx2_tim_evdev.c
@@ -10,6 +10,51 @@
 
 static struct rte_event_timer_adapter_ops otx2_tim_ops;
 
+static void
+tim_optimze_bkt_param(struct otx2_tim_ring *tim_ring)
+{
+	uint64_t tck_nsec;
+	uint32_t hbkts;
+	uint32_t lbkts;
+
+	hbkts = rte_align32pow2(tim_ring->nb_bkts);
+	tck_nsec = RTE_ALIGN_MUL_CEIL(tim_ring->max_tout / (hbkts - 1), 10);
+
+	if ((tck_nsec < TICK2NSEC(OTX2_TIM_MIN_TMO_TKS,
+				  tim_ring->tenns_clk_freq) ||
+	    hbkts > OTX2_TIM_MAX_BUCKETS))
+		hbkts = 0;
+
+	lbkts = rte_align32prevpow2(tim_ring->nb_bkts);
+	tck_nsec = RTE_ALIGN_MUL_CEIL((tim_ring->max_tout / (lbkts - 1)), 10);
+
+	if ((tck_nsec < TICK2NSEC(OTX2_TIM_MIN_TMO_TKS,
+				  tim_ring->tenns_clk_freq) ||
+	    lbkts > OTX2_TIM_MAX_BUCKETS))
+		lbkts = 0;
+
+	if (!hbkts && !lbkts)
+		return;
+
+	if (!hbkts) {
+		tim_ring->nb_bkts = lbkts;
+		goto end;
+	} else if (!lbkts) {
+		tim_ring->nb_bkts = hbkts;
+		goto end;
+	}
+
+	tim_ring->nb_bkts = (hbkts - tim_ring->nb_bkts) <
+		(tim_ring->nb_bkts - lbkts) ? hbkts : lbkts;
+end:
+	tim_ring->optimized = true;
+	tim_ring->tck_nsec = RTE_ALIGN_MUL_CEIL((tim_ring->max_tout /
+						(tim_ring->nb_bkts - 1)), 10);
+	otx2_tim_dbg("Optimized configured values");
+	otx2_tim_dbg("Nb_bkts  : %" PRIu32 "", tim_ring->nb_bkts);
+	otx2_tim_dbg("Tck_nsec : %" PRIu64 "", tim_ring->tck_nsec);
+}
+
 static int
 tim_chnk_pool_create(struct otx2_tim_ring *tim_ring,
 		     struct rte_event_timer_adapter_conf *rcfg)
@@ -159,8 +204,13 @@ otx2_tim_ring_create(struct rte_event_timer_adapter *adptr)
 
 	if (NSEC2TICK(RTE_ALIGN_MUL_CEIL(rcfg->timer_tick_ns, 10),
 		      rsp->tenns_clk) < OTX2_TIM_MIN_TMO_TKS) {
-		rc = -ERANGE;
-		goto rng_mem_err;
+		if (rcfg->flags & RTE_EVENT_TIMER_ADAPTER_F_ADJUST_RES)
+			rcfg->timer_tick_ns = TICK2NSEC(OTX2_TIM_MIN_TMO_TKS,
+					rsp->tenns_clk);
+		else {
+			rc = -ERANGE;
+			goto rng_mem_err;
+		}
 	}
 
 	tim_ring = rte_zmalloc("otx2_tim_prv", sizeof(struct otx2_tim_ring), 0);
@@ -183,6 +233,14 @@ otx2_tim_ring_create(struct rte_event_timer_adapter *adptr)
 							tim_ring->chunk_sz);
 	tim_ring->nb_chunk_slots = OTX2_TIM_NB_CHUNK_SLOTS(tim_ring->chunk_sz);
 
+	/* Try to optimize the bucket parameters. */
+	if ((rcfg->flags & RTE_EVENT_TIMER_ADAPTER_F_ADJUST_RES)) {
+		if (rte_is_power_of_2(tim_ring->nb_bkts))
+			tim_ring->optimized = true;
+		else
+			tim_optimze_bkt_param(tim_ring);
+	}
+
 	/* Create buckets. */
 	tim_ring->bkt = rte_zmalloc("otx2_tim_bucket", (tim_ring->nb_bkts) *
 				    sizeof(struct otx2_tim_bkt),
diff --git a/drivers/event/octeontx2/otx2_tim_evdev.h b/drivers/event/octeontx2/otx2_tim_evdev.h
index aaa4d93f5..fdd076ebd 100644
--- a/drivers/event/octeontx2/otx2_tim_evdev.h
+++ b/drivers/event/octeontx2/otx2_tim_evdev.h
@@ -17,6 +17,8 @@
 #define TIM_LF_RING_AURA		(0x0)
 #define TIM_LF_RING_BASE		(0x130)
 
+#define OTX2_MAX_TIM_RINGS		(256)
+#define OTX2_TIM_MAX_BUCKETS		(0xFFFFF)
 #define OTX2_TIM_RING_DEF_CHUNK_SZ	(4096)
 #define OTX2_TIM_CHUNK_ALIGNMENT	(16)
 #define OTX2_TIM_NB_CHUNK_SLOTS(sz)	(((sz) / OTX2_TIM_CHUNK_ALIGNMENT) - 1)
@@ -63,6 +65,7 @@ struct otx2_tim_ring {
 	struct rte_mempool *chunk_pool;
 	uint64_t tck_int;
 	uint8_t prod_type_sp;
+	uint8_t optimized;
 	uint8_t ena_dfb;
 	uint16_t ring_id;
 	uint32_t aura;
-- 
2.22.0



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