[dpdk-dev] [PATCH v3 32/42] event/octeontx2: add TIM IRQ handlers

pbhagavatula at marvell.com pbhagavatula at marvell.com
Fri Jun 28 20:23:43 CEST 2019


From: Pavan Nikhilesh <pbhagavatula at marvell.com>

Register and implement TIM IRQ handlers for error interrupts

Signed-off-by: Pavan Nikhilesh <pbhagavatula at marvell.com>
---
 drivers/event/octeontx2/otx2_evdev_irq.c | 97 ++++++++++++++++++++++++
 drivers/event/octeontx2/otx2_tim_evdev.c | 37 +++++++++
 drivers/event/octeontx2/otx2_tim_evdev.h | 14 ++++
 3 files changed, 148 insertions(+)

diff --git a/drivers/event/octeontx2/otx2_evdev_irq.c b/drivers/event/octeontx2/otx2_evdev_irq.c
index 7379bb17f..a2033646e 100644
--- a/drivers/event/octeontx2/otx2_evdev_irq.c
+++ b/drivers/event/octeontx2/otx2_evdev_irq.c
@@ -3,6 +3,7 @@
  */
 
 #include "otx2_evdev.h"
+#include "otx2_tim_evdev.h"
 
 static void
 sso_lf_irq(void *param)
@@ -173,3 +174,99 @@ sso_unregister_irqs(const struct rte_eventdev *event_dev)
 		ssow_lf_unregister_irq(event_dev, dev->ssow_msixoff[i], base);
 	}
 }
+
+static void
+tim_lf_irq(void *param)
+{
+	uintptr_t base = (uintptr_t)param;
+	uint64_t intr;
+	uint8_t ring;
+
+	ring = (base >> 12) & 0xFF;
+
+	intr = otx2_read64(base + TIM_LF_NRSPERR_INT);
+	otx2_err("TIM RING %d TIM_LF_NRSPERR_INT=0x%" PRIx64 "", ring, intr);
+	intr = otx2_read64(base + TIM_LF_RAS_INT);
+	otx2_err("TIM RING %d TIM_LF_RAS_INT=0x%" PRIx64 "", ring, intr);
+
+	/* Clear interrupt */
+	otx2_write64(intr, base + TIM_LF_NRSPERR_INT);
+	otx2_write64(intr, base + TIM_LF_RAS_INT);
+}
+
+static int
+tim_lf_register_irq(struct rte_pci_device *pci_dev, uint16_t tim_msixoff,
+		    uintptr_t base)
+{
+	struct rte_intr_handle *handle = &pci_dev->intr_handle;
+	int rc, vec;
+
+	vec = tim_msixoff + TIM_LF_INT_VEC_NRSPERR_INT;
+
+	/* Clear err interrupt */
+	otx2_write64(~0ull, base + TIM_LF_NRSPERR_INT);
+	/* Set used interrupt vectors */
+	rc = otx2_register_irq(handle, tim_lf_irq, (void *)base, vec);
+	/* Enable hw interrupt */
+	otx2_write64(~0ull, base + TIM_LF_NRSPERR_INT_ENA_W1S);
+
+	vec = tim_msixoff + TIM_LF_INT_VEC_RAS_INT;
+
+	/* Clear err interrupt */
+	otx2_write64(~0ull, base + TIM_LF_RAS_INT);
+	/* Set used interrupt vectors */
+	rc = otx2_register_irq(handle, tim_lf_irq, (void *)base, vec);
+	/* Enable hw interrupt */
+	otx2_write64(~0ull, base + TIM_LF_RAS_INT_ENA_W1S);
+
+	return rc;
+}
+
+static void
+tim_lf_unregister_irq(struct rte_pci_device *pci_dev, uint16_t tim_msixoff,
+		      uintptr_t base)
+{
+	struct rte_intr_handle *handle = &pci_dev->intr_handle;
+	int vec;
+
+	vec = tim_msixoff + TIM_LF_INT_VEC_NRSPERR_INT;
+
+	/* Clear err interrupt */
+	otx2_write64(~0ull, base + TIM_LF_NRSPERR_INT_ENA_W1C);
+	otx2_unregister_irq(handle, tim_lf_irq, (void *)base, vec);
+
+	vec = tim_msixoff + TIM_LF_INT_VEC_RAS_INT;
+
+	/* Clear err interrupt */
+	otx2_write64(~0ull, base + TIM_LF_RAS_INT_ENA_W1C);
+	otx2_unregister_irq(handle, tim_lf_irq, (void *)base, vec);
+}
+
+int
+tim_register_irq(uint16_t ring_id)
+{
+	struct otx2_tim_evdev *dev = tim_priv_get();
+	int rc = -EINVAL;
+	uintptr_t base;
+
+	if (dev->tim_msixoff[ring_id] == MSIX_VECTOR_INVALID) {
+		otx2_err("Invalid TIMLF MSIX offset[%d] vector: 0x%x",
+			 ring_id, dev->tim_msixoff[ring_id]);
+		goto fail;
+	}
+
+	base = dev->bar2 + (RVU_BLOCK_ADDR_TIM << 20 | ring_id << 12);
+	rc = tim_lf_register_irq(dev->pci_dev, dev->tim_msixoff[ring_id], base);
+fail:
+	return rc;
+}
+
+void
+tim_unregister_irq(uint16_t ring_id)
+{
+	struct otx2_tim_evdev *dev = tim_priv_get();
+	uintptr_t base;
+
+	base = dev->bar2 + (RVU_BLOCK_ADDR_TIM << 20 | ring_id << 12);
+	tim_lf_unregister_irq(dev->pci_dev, dev->tim_msixoff[ring_id], base);
+}
diff --git a/drivers/event/octeontx2/otx2_tim_evdev.c b/drivers/event/octeontx2/otx2_tim_evdev.c
index c0a692bb5..8324ded51 100644
--- a/drivers/event/octeontx2/otx2_tim_evdev.c
+++ b/drivers/event/octeontx2/otx2_tim_evdev.c
@@ -11,6 +11,24 @@
 
 static struct rte_event_timer_adapter_ops otx2_tim_ops;
 
+static inline int
+tim_get_msix_offsets(void)
+{
+	struct otx2_tim_evdev *dev = tim_priv_get();
+	struct otx2_mbox *mbox = dev->mbox;
+	struct msix_offset_rsp *msix_rsp;
+	int i, rc;
+
+	/* Get TIM MSIX vector offsets */
+	otx2_mbox_alloc_msg_msix_offset(mbox);
+	rc = otx2_mbox_process_msg(mbox, (void *)&msix_rsp);
+
+	for (i = 0; i < dev->nb_rings; i++)
+		dev->tim_msixoff[i] = msix_rsp->timlf_msixoff[i];
+
+	return rc;
+}
+
 static void
 tim_optimze_bkt_param(struct otx2_tim_ring *tim_ring)
 {
@@ -288,6 +306,10 @@ otx2_tim_ring_create(struct rte_event_timer_adapter *adptr)
 	tim_ring->base = dev->bar2 +
 		(RVU_BLOCK_ADDR_TIM << 20 | tim_ring->ring_id << 12);
 
+	rc = tim_register_irq(tim_ring->ring_id);
+	if (rc < 0)
+		goto chnk_mem_err;
+
 	otx2_write64((uint64_t)tim_ring->bkt,
 		     tim_ring->base + TIM_LF_RING_BASE);
 	otx2_write64(tim_ring->aura, tim_ring->base + TIM_LF_RING_AURA);
@@ -316,6 +338,8 @@ otx2_tim_ring_free(struct rte_event_timer_adapter *adptr)
 	if (dev == NULL)
 		return -ENODEV;
 
+	tim_unregister_irq(tim_ring->ring_id);
+
 	req = otx2_mbox_alloc_msg_tim_lf_free(dev->mbox);
 	req->ring = tim_ring->ring_id;
 
@@ -379,6 +403,7 @@ void
 otx2_tim_init(struct rte_pci_device *pci_dev, struct otx2_dev *cmn_dev)
 {
 	struct rsrc_attach_req *atch_req;
+	struct rsrc_detach_req *dtch_req;
 	struct free_rsrcs_rsp *rsrc_cnt;
 	const struct rte_memzone *mz;
 	struct otx2_tim_evdev *dev;
@@ -426,6 +451,12 @@ otx2_tim_init(struct rte_pci_device *pci_dev, struct otx2_dev *cmn_dev)
 		goto mz_free;
 	}
 
+	rc = tim_get_msix_offsets();
+	if (rc < 0) {
+		otx2_err("Unable to get MSIX offsets for TIM.");
+		goto detach;
+	}
+
 	if (dev->chunk_slots &&
 	    dev->chunk_slots <= OTX2_TIM_MAX_CHUNK_SLOTS &&
 	    dev->chunk_slots >= OTX2_TIM_MIN_CHUNK_SLOTS) {
@@ -437,6 +468,12 @@ otx2_tim_init(struct rte_pci_device *pci_dev, struct otx2_dev *cmn_dev)
 
 	return;
 
+detach:
+	dtch_req = otx2_mbox_alloc_msg_detach_resources(dev->mbox);
+	dtch_req->partial = true;
+	dtch_req->timlfs = true;
+
+	otx2_mbox_process(dev->mbox);
 mz_free:
 	rte_memzone_free(mz);
 }
diff --git a/drivers/event/octeontx2/otx2_tim_evdev.h b/drivers/event/octeontx2/otx2_tim_evdev.h
index 9636d8414..aac7dc711 100644
--- a/drivers/event/octeontx2/otx2_tim_evdev.h
+++ b/drivers/event/octeontx2/otx2_tim_evdev.h
@@ -16,6 +16,14 @@
 
 #define TIM_LF_RING_AURA		(0x0)
 #define TIM_LF_RING_BASE		(0x130)
+#define TIM_LF_NRSPERR_INT		(0x200)
+#define TIM_LF_NRSPERR_INT_W1S		(0x208)
+#define TIM_LF_NRSPERR_INT_ENA_W1S	(0x210)
+#define TIM_LF_NRSPERR_INT_ENA_W1C	(0x218)
+#define TIM_LF_RAS_INT			(0x300)
+#define TIM_LF_RAS_INT_W1S		(0x308)
+#define TIM_LF_RAS_INT_ENA_W1S		(0x310)
+#define TIM_LF_RAS_INT_ENA_W1C		(0x318)
 
 #define OTX2_MAX_TIM_RINGS		(256)
 #define OTX2_TIM_MAX_BUCKETS		(0xFFFFF)
@@ -61,6 +69,8 @@ struct otx2_tim_evdev {
 	/* Dev args */
 	uint8_t disable_npa;
 	uint16_t chunk_slots;
+	/* MSIX offsets */
+	uint16_t tim_msixoff[OTX2_MAX_TIM_RINGS];
 };
 
 struct otx2_tim_ring {
@@ -103,4 +113,8 @@ int otx2_tim_caps_get(const struct rte_eventdev *dev, uint64_t flags,
 void otx2_tim_init(struct rte_pci_device *pci_dev, struct otx2_dev *cmn_dev);
 void otx2_tim_fini(void);
 
+/* TIM IRQ */
+int tim_register_irq(uint16_t ring_id);
+void tim_unregister_irq(uint16_t ring_id);
+
 #endif /* __OTX2_TIM_EVDEV_H__ */
-- 
2.22.0



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