[dpdk-dev] [PATCH 4/4] test: fix memory barrier test failure on power CPUs

[Thomas Monjalon]

Hi,

01/05/2019 00:33, David Christensen:
> The memory barrier test fails on IBM Power 9 systems.  Add additional
> barriers to accommodate the weakly ordered model used on Power CPUs.
> 
> Signed-off-by: David Christensen <drc at linux.vnet.ibm.com>
[...]
> --- a/app/test/test_barrier.c
> +++ b/app/test/test_barrier.c
> @@ -36,7 +36,7 @@
>  #include "test.h"
>  
>  #define ADD_MAX		8
> -#define ITER_MAX	0x100000000
> +#define ITER_MAX	0x1000000

This is a revert of a change done in patch 3.

> @@ -92,12 +92,19 @@ struct lcore_plock_test {
>  	other = self ^ 1;
>  
>  	l->flag[self] = 1;
> +#ifdef RTE_ARCH_PPC_64
> +	rte_smp_wmb();
> +#endif

You should not have such #ifdef in a test case
supposed to run on all architectures with the same code.
What can be fixed in EAL?