[dpdk-dev] [dpdk-stable] [PATCH] net/iavf: fix queue interrupt for ICE

[Kevin Traynor]

On 18/04/2019 05:58, Wei Zhao wrote:
> Enable CLEARPBA bit is required by ice NIC of A0/A1 version to
> enable Tx and Rx queue interrupt.
> Also enable CLEARPBA bit does no impact on IAVF behaviour when be
> hosted by other devices, so we can make it as default.
> 
> Fixes: d6bde6b5eae9 ("net/avf: enable Rx interrupt")

The Fixes commit is in 18.11 stable but ice is not. If this is just for
ice as commit msg suggests, then it is not needed for 18.11 stable
branch. Please let me know if it's needed for some other reason on 18.11
branch.

thanks,
Kevin.

> Cc: stable at dpdk.org
> 
> Signed-off-by: Wei Zhao <wei.zhao1 at intel.com>
> ---
>  drivers/net/iavf/iavf_ethdev.c | 2 ++
>  1 file changed, 2 insertions(+)
> 
> diff --git a/drivers/net/iavf/iavf_ethdev.c b/drivers/net/iavf/iavf_ethdev.c
> index 846e604..57819dd 100644
> --- a/drivers/net/iavf/iavf_ethdev.c
> +++ b/drivers/net/iavf/iavf_ethdev.c
> @@ -1015,11 +1015,13 @@ iavf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
>  		PMD_DRV_LOG(INFO, "MISC is also enabled for control");
>  		IAVF_WRITE_REG(hw, IAVFINT_DYN_CTL01,
>  			      IAVFINT_DYN_CTL01_INTENA_MASK |
> +			      IAVFINT_DYN_CTL01_CLEARPBA_MASK |
>  			      IAVFINT_DYN_CTL01_ITR_INDX_MASK);
>  	} else {
>  		IAVF_WRITE_REG(hw,
>  			      IAVFINT_DYN_CTLN1(msix_intr - IAVF_RX_VEC_START),
>  			      IAVFINT_DYN_CTLN1_INTENA_MASK |
> +			      IAVFINT_DYN_CTL01_CLEARPBA_MASK |
>  			      IAVFINT_DYN_CTLN1_ITR_INDX_MASK);
>  	}
>  
>