[dpdk-dev] Mbuf memory alignment constraints for (micro)architectures

[David Christensen]

> # Is PPC and other ARM SoC has formula (B)  to compute DRAM channel distribution ? or
> Is it specific to x86? That would define where the hooks needs to added to have proper fix.
The Power 9 chip has eight memory channels, each with a dedicated memory 
controller unit (MCU).  The MCUs can be configured into one or more 
address interleave groups (with 1, 2, 3, 4, 6, or 8 MCUs), with a 
programmable interleave granularity of 128B to 32KB.  Trying to find 
more info on how to access this configuration data and expose it to the 
DPDK.

Dave