[dpdk-dev] [PATCH 2/2] net/mlx5: fix Tx CQ doorbell synchronization on aarch64

[Phil Yang]

For the weaker memory model processors, the compiler barrier is not
sufficient to guarantee the coherent memory update be observed by
I/O device. It needs the coherent I/O memory barrier to enforce the
ordering of Tx completion queue doorbell operation.

Fixes: da1df1ccabad ("net/mlx5: fix completion queue drain loop")
Cc: stable at dpdk.org

Suggested-by: Gavin Hu <gavin.hu at arm.com>
Signed-off-by: Phil Yang <phil.yang at arm.com>
Reviewed-by: Gavin Hu <gavin.hu at arm.com>
---
 drivers/net/mlx5/mlx5_rxtx.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/net/mlx5/mlx5_rxtx.c b/drivers/net/mlx5/mlx5_rxtx.c
index 4c01187..c11148b 100644
--- a/drivers/net/mlx5/mlx5_rxtx.c
+++ b/drivers/net/mlx5/mlx5_rxtx.c
@@ -2042,7 +2042,7 @@ mlx5_tx_comp_flush(struct mlx5_txq_data *restrict txq,
 	} else {
 		return;
 	}
-	rte_compiler_barrier();
+	rte_cio_wmb();
 	*txq->cq_db = rte_cpu_to_be_32(txq->cq_ci);
 	if (likely(tail != txq->elts_tail)) {
 		mlx5_tx_free_elts(txq, tail, olx);
-- 
2.7.4