[dpdk-dev] [PATCH v2 1/5] net/i40e: use relaxed and remove duplicate barrier
Gavin Hu (Arm Technology China)
Gavin.Hu at arm.com
Tue Sep 17 04:07:50 CEST 2019
Hi Qi,
> -----Original Message-----
> From: Zhang, Qi Z <qi.z.zhang at intel.com>
> Sent: Tuesday, September 17, 2019 9:53 AM
> To: Gavin Hu (Arm Technology China) <Gavin.Hu at arm.com>; dev at dpdk.org
> Cc: nd <nd at arm.com>; thomas at monjalon.net; Richardson, Bruce
> <bruce.richardson at intel.com>; Liu, Yong <yong.liu at intel.com>; Wang, Yinan
> <yinan.wang at intel.com>; ajit.khaparde at broadcom.com;
> somnath.kotur at broadcom.com; Honnappa Nagarahalli
> <Honnappa.Nagarahalli at arm.com>; Ruifeng Wang (Arm Technology China)
> <Ruifeng.Wang at arm.com>; Steve Capper <Steve.Capper at arm.com>
> Subject: RE: [dpdk-dev] [PATCH v2 1/5] net/i40e: use relaxed and remove
> duplicate barrier
>
>
>
> > -----Original Message-----
> > From: dev [mailto:dev-bounces at dpdk.org] On Behalf Of Gavin Hu
> > Sent: Monday, September 16, 2019 7:27 PM
> > To: dev at dpdk.org
> > Cc: nd at arm.com; thomas at monjalon.net; Richardson, Bruce
> > <bruce.richardson at intel.com>; Liu, Yong <yong.liu at intel.com>; Wang,
> Yinan
> > <yinan.wang at intel.com>; ajit.khaparde at broadcom.com;
> > somnath.kotur at broadcom.com; Honnappa.Nagarahalli at arm.com;
> > ruifeng.wang at arm.com; steve.capper at arm.com
> > Subject: [dpdk-dev] [PATCH v2 1/5] net/i40e: use relaxed and remove
> > duplicate barrier
> >
> > To guarantee the orderings of successive stores to CIO and MMIO memory,
> a
> > lighter weight rte_io_wmb [1] can be used instead of rte_wmb, and since
> the
> > I40E_PCI_REG_WRITE API already has an inclusive rte_io_wmb, this explicit
> call
> > can be even saved.
> >
> > [1] http://git.dpdk.org/dpdk/tree/lib/librte_eal/common/include/generic/
> > rte_atomic.h#n98
> >
> > Signed-off-by: Gavin Hu <gavin.hu at arm.com>
>
> Can you also capture the one at the tail of i40e_xmit_pkts?
Thanks for your review, I will fix this in next version.
>
> Otherwise
> Acked-by: Qi Zhang <qi.z.zhang at intel.com>
>
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