[dpdk-dev] [PATCH v5] net/ipn3ke: setup MTU when HW init

[Xu, Rosen]

Hi,

> -----Original Message-----
> From: Pei, Andy
> Sent: Wednesday, September 04, 2019 2:53
> To: dev at dpdk.org
> Cc: Pei, Andy <andy.pei at intel.com>; Zhang, Qi Z <qi.z.zhang at intel.com>;
> Yigit, Ferruh <ferruh.yigit at intel.com>; Xu, Rosen <rosen.xu at intel.com>; Ye,
> Xiaolong <xiaolong.ye at intel.com>
> Subject: [PATCH v5] net/ipn3ke: setup MTU when HW init
> 
> set up mtu to the minimun in tx mtu, rx mtu and
> IPN3KE_MAC_FRAME_SIZE_MAX.
> 
> Signed-off-by: Andy Pei <andy.pei at intel.com>
> ---
> 
> Cc: qi.z.zhang at intel.com
> Cc: ferruh.yigit at intel.com
> Cc: rosen.xu at intel.com
> Cc: xiaolong.ye at intel.com
> 
> v2:
> modify low bound and upper bound.
> 
> v3:
> delete unnecessary MACROs.
> extract the duplicated code to a common function.
> 
> v4:
> delete unnecessary MACROs.
> extract the duplicated code to a common function.
> 
> v5:
> Not to start the arguments in a separate line.
> 
> drivers/net/ipn3ke/ipn3ke_ethdev.c | 86
> ++++++++++++++++++++++++++++++++++++++
>  drivers/net/ipn3ke/ipn3ke_ethdev.h |  6 +++
>  2 files changed, 92 insertions(+)
> 
> diff --git a/drivers/net/ipn3ke/ipn3ke_ethdev.c
> b/drivers/net/ipn3ke/ipn3ke_ethdev.c
> index c226d63..28d8aaf 100644
> --- a/drivers/net/ipn3ke/ipn3ke_ethdev.c
> +++ b/drivers/net/ipn3ke/ipn3ke_ethdev.c
> @@ -209,6 +209,89 @@
>  	return 0;
>  }
> 
> +static uint32_t
> +ipn3ke_mtu_cal(uint32_t tx, uint32_t rx) {
> +	uint32_t tmp;
> +	tmp = RTE_MIN(tx, rx);
> +	tmp = RTE_MAX(tmp, (uint32_t)RTE_ETHER_MIN_MTU);
> +	tmp = RTE_MIN(tmp, (uint32_t)(IPN3KE_MAC_FRAME_SIZE_MAX -
> +		IPN3KE_ETH_OVERHEAD));
> +	return tmp;
> +}
> +
> +static void
> +ipn3ke_mtu_set(struct ipn3ke_hw *hw, uint32_t mac_num,
> +	uint32_t eth_group_sel, uint32_t txaddr, uint32_t rxaddr) {
> +	uint32_t tx;
> +	uint32_t rx;
> +	uint32_t tmp;
> +
> +	if (!(*hw->f_mac_read) || !(*hw->f_mac_write))
> +		return;
> +
> +	(*hw->f_mac_read)(hw,
> +			&tx,
> +			txaddr,
> +			mac_num,
> +			eth_group_sel);
> +
> +	(*hw->f_mac_read)(hw,
> +			&rx,
> +			rxaddr,
> +			mac_num,
> +			eth_group_sel);
> +
> +	tmp = ipn3ke_mtu_cal(tx, rx);
> +
> +	(*hw->f_mac_write)(hw,
> +			tmp,
> +			txaddr,
> +			mac_num,
> +			eth_group_sel);
> +
> +	(*hw->f_mac_write)(hw,
> +			tmp,
> +			rxaddr,
> +			mac_num,
> +			eth_group_sel);
> +}
> +
> +static void
> +ipn3ke_10G_mtu_setup(struct ipn3ke_hw *hw, uint32_t mac_num,
> +	uint32_t eth_group_sel)
> +{
> +	ipn3ke_mtu_set(hw, mac_num, eth_group_sel,
> +		IPN3KE_10G_TX_FRAME_MAXLENGTH,
> IPN3KE_10G_RX_FRAME_MAXLENGTH); }
> +
> +static void
> +ipn3ke_25G_mtu_setup(struct ipn3ke_hw *hw, uint32_t mac_num,
> +	uint32_t eth_group_sel)
> +{
> +	ipn3ke_mtu_set(hw, mac_num, eth_group_sel,
> +		IPN3KE_25G_MAX_TX_SIZE_CONFIG,
> IPN3KE_25G_MAX_RX_SIZE_CONFIG); }
> +
> +static void
> +ipn3ke_mtu_setup(struct ipn3ke_hw *hw)
> +{
> +	int i;
> +	if (hw->retimer.mac_type ==
> IFPGA_RAWDEV_RETIMER_MAC_TYPE_10GE_XFI) {
> +		for (i = 0; i < hw->port_num; i++) {
> +			ipn3ke_10G_mtu_setup(hw, i, 0);
> +			ipn3ke_10G_mtu_setup(hw, i, 1);
> +		}
> +	} else if (hw->retimer.mac_type ==
> +
> 	IFPGA_RAWDEV_RETIMER_MAC_TYPE_25GE_25GAUI) {
> +		for (i = 0; i < hw->port_num; i++) {
> +			ipn3ke_25G_mtu_setup(hw, i, 0);
> +			ipn3ke_25G_mtu_setup(hw, i, 1);
> +		}
> +	}
> +}
> +
>  static int
>  ipn3ke_hw_init(struct rte_afu_device *afu_dev,
>  	struct ipn3ke_hw *hw)
> @@ -303,6 +386,9 @@
>  		}
>  	}
> 
> +	/* init mtu */
> +	ipn3ke_mtu_setup(hw);
> +
>  	ret = rte_eth_switch_domain_alloc(&hw->switch_domain_id);
>  	if (ret)
>  		IPN3KE_AFU_PMD_WARN("failed to allocate switch domain
> for device %d", diff --git a/drivers/net/ipn3ke/ipn3ke_ethdev.h
> b/drivers/net/ipn3ke/ipn3ke_ethdev.h
> index c7b336b..fc45826 100644
> --- a/drivers/net/ipn3ke/ipn3ke_ethdev.h
> +++ b/drivers/net/ipn3ke/ipn3ke_ethdev.h
> @@ -654,6 +654,12 @@ static inline void _ipn3ke_indrct_write(struct
> ipn3ke_hw *hw,  #define IPN3KE_MAC_RX_FRAME_MAXLENGTH_MASK \
>  	IPN3KE_MASK(0xFFFF,
> IPN3KE_MAC_RX_FRAME_MAXLENGTH_SHIFT)
> 
> +#define IPN3KE_25G_MAX_TX_SIZE_CONFIG                                0x407
> +#define IPN3KE_25G_MAX_RX_SIZE_CONFIG                                0x506
> +
> +#define IPN3KE_10G_TX_FRAME_MAXLENGTH                                0x002C
> +#define IPN3KE_10G_RX_FRAME_MAXLENGTH                                0x00AE
> +
>  #define IPN3KE_REGISTER_WIDTH                                        32
> 
>  /*Bits[2:0]: Configuration of TX statistics counters:
> --
> 1.8.3.1

Acked-by: Rosen Xu <rosen.xu at intel.com>