[dpdk-dev] [PATCH 6/9] net/qede/base: move dmae code to HSI
Rasesh Mody
rmody at marvell.com
Mon Sep 30 04:49:18 CEST 2019
Move DMA engine (DMAE) structures from base driver to HSI module.
Use DMAE_PARAMS_* in place of ECORE_DMAE_FLAG_*.
Enforce SET_FIELD() macro where appropriate.
Signed-off-by: Rasesh Mody <rmody at marvell.com>
---
drivers/net/qede/base/ecore_dev.c | 12 ++--
drivers/net/qede/base/ecore_dev_api.h | 92 ------------------------
drivers/net/qede/base/ecore_hsi_common.h | 58 ++++++++++++++-
drivers/net/qede/base/ecore_hw.c | 52 ++++++++------
drivers/net/qede/base/ecore_hw.h | 88 +++++++++++++++++------
drivers/net/qede/base/ecore_init_ops.c | 4 +-
drivers/net/qede/base/ecore_sriov.c | 23 +++---
7 files changed, 174 insertions(+), 155 deletions(-)
diff --git a/drivers/net/qede/base/ecore_dev.c b/drivers/net/qede/base/ecore_dev.c
index 749aea4e8..2c135afd2 100644
--- a/drivers/net/qede/base/ecore_dev.c
+++ b/drivers/net/qede/base/ecore_dev.c
@@ -950,7 +950,7 @@ ecore_llh_access_filter(struct ecore_hwfn *p_hwfn,
bool b_write_access)
{
u8 pfid = ECORE_PFID_BY_PPFID(p_hwfn, abs_ppfid);
- struct ecore_dmae_params params;
+ struct dmae_params params;
enum _ecore_status_t rc;
u32 addr;
@@ -973,15 +973,15 @@ ecore_llh_access_filter(struct ecore_hwfn *p_hwfn,
OSAL_MEMSET(¶ms, 0, sizeof(params));
if (b_write_access) {
- params.flags = ECORE_DMAE_FLAG_PF_DST;
- params.dst_pfid = pfid;
+ SET_FIELD(params.flags, DMAE_PARAMS_DST_PF_VALID, 0x1);
+ params.dst_pf_id = pfid;
rc = ecore_dmae_host2grc(p_hwfn, p_ptt,
(u64)(osal_uintptr_t)&p_details->value,
addr, 2 /* size_in_dwords */, ¶ms);
} else {
- params.flags = ECORE_DMAE_FLAG_PF_SRC |
- ECORE_DMAE_FLAG_COMPLETION_DST;
- params.src_pfid = pfid;
+ SET_FIELD(params.flags, DMAE_PARAMS_SRC_PF_VALID, 0x1);
+ SET_FIELD(params.flags, DMAE_PARAMS_COMPLETION_DST, 0x1);
+ params.src_pf_id = pfid;
rc = ecore_dmae_grc2host(p_hwfn, p_ptt, addr,
(u64)(osal_uintptr_t)&p_details->value,
2 /* size_in_dwords */, ¶ms);
diff --git a/drivers/net/qede/base/ecore_dev_api.h b/drivers/net/qede/base/ecore_dev_api.h
index a99888097..4d5cc1a0f 100644
--- a/drivers/net/qede/base/ecore_dev_api.h
+++ b/drivers/net/qede/base/ecore_dev_api.h
@@ -415,98 +415,6 @@ struct ecore_eth_stats {
};
};
-enum ecore_dmae_address_type_t {
- ECORE_DMAE_ADDRESS_HOST_VIRT,
- ECORE_DMAE_ADDRESS_HOST_PHYS,
- ECORE_DMAE_ADDRESS_GRC
-};
-
-/* value of flags If ECORE_DMAE_FLAG_RW_REPL_SRC flag is set and the
- * source is a block of length DMAE_MAX_RW_SIZE and the
- * destination is larger, the source block will be duplicated as
- * many times as required to fill the destination block. This is
- * used mostly to write a zeroed buffer to destination address
- * using DMA
- */
-#define ECORE_DMAE_FLAG_RW_REPL_SRC 0x00000001
-#define ECORE_DMAE_FLAG_VF_SRC 0x00000002
-#define ECORE_DMAE_FLAG_VF_DST 0x00000004
-#define ECORE_DMAE_FLAG_COMPLETION_DST 0x00000008
-#define ECORE_DMAE_FLAG_PORT 0x00000010
-#define ECORE_DMAE_FLAG_PF_SRC 0x00000020
-#define ECORE_DMAE_FLAG_PF_DST 0x00000040
-
-struct ecore_dmae_params {
- u32 flags; /* consists of ECORE_DMAE_FLAG_* values */
- u8 src_vfid;
- u8 dst_vfid;
- u8 port_id;
- u8 src_pfid;
- u8 dst_pfid;
-};
-
-/**
- * @brief ecore_dmae_host2grc - copy data from source addr to
- * dmae registers using the given ptt
- *
- * @param p_hwfn
- * @param p_ptt
- * @param source_addr
- * @param grc_addr (dmae_data_offset)
- * @param size_in_dwords
- * @param p_params (default parameters will be used in case of OSAL_NULL)
- *
- * @return enum _ecore_status_t
- */
-enum _ecore_status_t
-ecore_dmae_host2grc(struct ecore_hwfn *p_hwfn,
- struct ecore_ptt *p_ptt,
- u64 source_addr,
- u32 grc_addr,
- u32 size_in_dwords,
- struct ecore_dmae_params *p_params);
-
-/**
- * @brief ecore_dmae_grc2host - Read data from dmae data offset
- * to source address using the given ptt
- *
- * @param p_ptt
- * @param grc_addr (dmae_data_offset)
- * @param dest_addr
- * @param size_in_dwords
- * @param p_params (default parameters will be used in case of OSAL_NULL)
- *
- * @return enum _ecore_status_t
- */
-enum _ecore_status_t
-ecore_dmae_grc2host(struct ecore_hwfn *p_hwfn,
- struct ecore_ptt *p_ptt,
- u32 grc_addr,
- dma_addr_t dest_addr,
- u32 size_in_dwords,
- struct ecore_dmae_params *p_params);
-
-/**
- * @brief ecore_dmae_host2host - copy data from to source address
- * to a destination address (for SRIOV) using the given ptt
- *
- * @param p_hwfn
- * @param p_ptt
- * @param source_addr
- * @param dest_addr
- * @param size_in_dwords
- * @param p_params (default parameters will be used in case of OSAL_NULL)
- *
- * @return enum _ecore_status_t
- */
-enum _ecore_status_t
-ecore_dmae_host2host(struct ecore_hwfn *p_hwfn,
- struct ecore_ptt *p_ptt,
- dma_addr_t source_addr,
- dma_addr_t dest_addr,
- u32 size_in_dwords,
- struct ecore_dmae_params *p_params);
-
/**
* @brief ecore_chain_alloc - Allocate and initialize a chain
*
diff --git a/drivers/net/qede/base/ecore_hsi_common.h b/drivers/net/qede/base/ecore_hsi_common.h
index 7a94ed506..8fa200033 100644
--- a/drivers/net/qede/base/ecore_hsi_common.h
+++ b/drivers/net/qede/base/ecore_hsi_common.h
@@ -1953,7 +1953,11 @@ struct dmae_cmd {
__le16 crc16 /* crc16 result */;
__le16 crc16_c /* crc16_c result */;
__le16 crc10 /* crc_t10 result */;
- __le16 reserved;
+ __le16 error_bit_reserved;
+#define DMAE_CMD_ERROR_BIT_MASK 0x1 /* Error bit */
+#define DMAE_CMD_ERROR_BIT_SHIFT 0
+#define DMAE_CMD_RESERVED_MASK 0x7FFF
+#define DMAE_CMD_RESERVED_SHIFT 1
__le16 xsum16 /* checksum16 result */;
__le16 xsum8 /* checksum8 result */;
};
@@ -2017,6 +2021,58 @@ enum dmae_cmd_src_enum {
};
+/*
+ * DMAE parameters
+ */
+struct dmae_params {
+ __le32 flags;
+/* If set and the source is a block of length DMAE_MAX_RW_SIZE and the
+ * destination is larger, the source block will be duplicated as many
+ * times as required to fill the destination block. This is used mostly
+ * to write a zeroed buffer to destination address using DMA
+ */
+#define DMAE_PARAMS_RW_REPL_SRC_MASK 0x1
+#define DMAE_PARAMS_RW_REPL_SRC_SHIFT 0
+/* If set, the source is a VF, and the source VF ID is taken from the
+ * src_vf_id parameter.
+ */
+#define DMAE_PARAMS_SRC_VF_VALID_MASK 0x1
+#define DMAE_PARAMS_SRC_VF_VALID_SHIFT 1
+/* If set, the destination is a VF, and the destination VF ID is taken
+ * from the dst_vf_id parameter.
+ */
+#define DMAE_PARAMS_DST_VF_VALID_MASK 0x1
+#define DMAE_PARAMS_DST_VF_VALID_SHIFT 2
+/* If set, a completion is sent to the destination function.
+ * Otherwise its sent to the source function.
+ */
+#define DMAE_PARAMS_COMPLETION_DST_MASK 0x1
+#define DMAE_PARAMS_COMPLETION_DST_SHIFT 3
+/* If set, the port ID is taken from the port_id parameter.
+ * Otherwise, the current port ID is used.
+ */
+#define DMAE_PARAMS_PORT_VALID_MASK 0x1
+#define DMAE_PARAMS_PORT_VALID_SHIFT 4
+/* If set, the source PF ID is taken from the src_pf_id parameter.
+ * Otherwise, the current PF ID is used.
+ */
+#define DMAE_PARAMS_SRC_PF_VALID_MASK 0x1
+#define DMAE_PARAMS_SRC_PF_VALID_SHIFT 5
+/* If set, the destination PF ID is taken from the dst_pf_id parameter.
+ * Otherwise, the current PF ID is used
+ */
+#define DMAE_PARAMS_DST_PF_VALID_MASK 0x1
+#define DMAE_PARAMS_DST_PF_VALID_SHIFT 6
+#define DMAE_PARAMS_RESERVED_MASK 0x1FFFFFF
+#define DMAE_PARAMS_RESERVED_SHIFT 7
+ u8 src_vf_id /* Source VF ID, valid only if src_vf_valid is set */;
+ u8 dst_vf_id /* Destination VF ID, valid only if dst_vf_valid is set */;
+ u8 port_id /* Port ID, valid only if port_valid is set */;
+ u8 src_pf_id /* Source PF ID, valid only if src_pf_valid is set */;
+ u8 dst_pf_id /* Destination PF ID, valid only if dst_pf_valid is set */;
+ u8 reserved1;
+ __le16 reserved2;
+};
struct fw_asserts_ram_section {
diff --git a/drivers/net/qede/base/ecore_hw.c b/drivers/net/qede/base/ecore_hw.c
index 72cd7e9c3..6a79db52e 100644
--- a/drivers/net/qede/base/ecore_hw.c
+++ b/drivers/net/qede/base/ecore_hw.c
@@ -453,14 +453,15 @@ u32 ecore_vfid_to_concrete(struct ecore_hwfn *p_hwfn, u8 vfid)
/* DMAE */
#define ECORE_DMAE_FLAGS_IS_SET(params, flag) \
- ((params) != OSAL_NULL && ((params)->flags & ECORE_DMAE_FLAG_##flag))
+ ((params) != OSAL_NULL && \
+ GET_FIELD((params)->flags, DMAE_PARAMS_##flag))
static void ecore_dmae_opcode(struct ecore_hwfn *p_hwfn,
const u8 is_src_type_grc,
const u8 is_dst_type_grc,
- struct ecore_dmae_params *p_params)
+ struct dmae_params *p_params)
{
- u8 src_pfid, dst_pfid, port_id;
+ u8 src_pf_id, dst_pf_id, port_id;
u16 opcode_b = 0;
u32 opcode = 0;
@@ -468,19 +469,19 @@ static void ecore_dmae_opcode(struct ecore_hwfn *p_hwfn,
* 0- The source is the PCIe
* 1- The source is the GRC.
*/
- opcode |= (is_src_type_grc ? DMAE_CMD_SRC_MASK_GRC
- : DMAE_CMD_SRC_MASK_PCIE) << DMAE_CMD_SRC_SHIFT;
- src_pfid = ECORE_DMAE_FLAGS_IS_SET(p_params, PF_SRC) ?
- p_params->src_pfid : p_hwfn->rel_pf_id;
- opcode |= (src_pfid & DMAE_CMD_SRC_PF_ID_MASK) <<
+ opcode |= (is_src_type_grc ? dmae_cmd_src_grc : dmae_cmd_src_pcie) <<
+ DMAE_CMD_SRC_SHIFT;
+ src_pf_id = ECORE_DMAE_FLAGS_IS_SET(p_params, SRC_PF_VALID) ?
+ p_params->src_pf_id : p_hwfn->rel_pf_id;
+ opcode |= (src_pf_id & DMAE_CMD_SRC_PF_ID_MASK) <<
DMAE_CMD_SRC_PF_ID_SHIFT;
/* The destination of the DMA can be: 0-None 1-PCIe 2-GRC 3-None */
- opcode |= (is_dst_type_grc ? DMAE_CMD_DST_MASK_GRC
- : DMAE_CMD_DST_MASK_PCIE) << DMAE_CMD_DST_SHIFT;
- dst_pfid = ECORE_DMAE_FLAGS_IS_SET(p_params, PF_DST) ?
- p_params->dst_pfid : p_hwfn->rel_pf_id;
- opcode |= (dst_pfid & DMAE_CMD_DST_PF_ID_MASK) <<
+ opcode |= (is_dst_type_grc ? dmae_cmd_dst_grc : dmae_cmd_dst_pcie) <<
+ DMAE_CMD_DST_SHIFT;
+ dst_pf_id = ECORE_DMAE_FLAGS_IS_SET(p_params, DST_PF_VALID) ?
+ p_params->dst_pf_id : p_hwfn->rel_pf_id;
+ opcode |= (dst_pf_id & DMAE_CMD_DST_PF_ID_MASK) <<
DMAE_CMD_DST_PF_ID_SHIFT;
/* DMAE_E4_TODO need to check which value to specify here. */
@@ -501,7 +502,7 @@ static void ecore_dmae_opcode(struct ecore_hwfn *p_hwfn,
*/
opcode |= DMAE_CMD_ENDIANITY << DMAE_CMD_ENDIANITY_MODE_SHIFT;
- port_id = (ECORE_DMAE_FLAGS_IS_SET(p_params, PORT)) ?
+ port_id = (ECORE_DMAE_FLAGS_IS_SET(p_params, PORT_VALID)) ?
p_params->port_id : p_hwfn->port_id;
opcode |= port_id << DMAE_CMD_PORT_ID_SHIFT;
@@ -512,16 +513,16 @@ static void ecore_dmae_opcode(struct ecore_hwfn *p_hwfn,
opcode |= DMAE_CMD_DST_ADDR_RESET_MASK << DMAE_CMD_DST_ADDR_RESET_SHIFT;
/* SRC/DST VFID: all 1's - pf, otherwise VF id */
- if (ECORE_DMAE_FLAGS_IS_SET(p_params, VF_SRC)) {
+ if (ECORE_DMAE_FLAGS_IS_SET(p_params, SRC_VF_VALID)) {
opcode |= (1 << DMAE_CMD_SRC_VF_ID_VALID_SHIFT);
- opcode_b |= (p_params->src_vfid << DMAE_CMD_SRC_VF_ID_SHIFT);
+ opcode_b |= (p_params->src_vf_id << DMAE_CMD_SRC_VF_ID_SHIFT);
} else {
opcode_b |= (DMAE_CMD_SRC_VF_ID_MASK <<
DMAE_CMD_SRC_VF_ID_SHIFT);
}
- if (ECORE_DMAE_FLAGS_IS_SET(p_params, VF_DST)) {
+ if (ECORE_DMAE_FLAGS_IS_SET(p_params, DST_VF_VALID)) {
opcode |= 1 << DMAE_CMD_DST_VF_ID_VALID_SHIFT;
- opcode_b |= p_params->dst_vfid << DMAE_CMD_DST_VF_ID_SHIFT;
+ opcode_b |= p_params->dst_vf_id << DMAE_CMD_DST_VF_ID_SHIFT;
} else {
opcode_b |= DMAE_CMD_DST_VF_ID_MASK << DMAE_CMD_DST_VF_ID_SHIFT;
}
@@ -716,6 +717,12 @@ static enum _ecore_status_t ecore_dmae_operation_wait(struct ecore_hwfn *p_hwfn)
return ecore_status;
}
+enum ecore_dmae_address_type {
+ ECORE_DMAE_ADDRESS_HOST_VIRT,
+ ECORE_DMAE_ADDRESS_HOST_PHYS,
+ ECORE_DMAE_ADDRESS_GRC
+};
+
static enum _ecore_status_t
ecore_dmae_execute_sub_operation(struct ecore_hwfn *p_hwfn,
struct ecore_ptt *p_ptt,
@@ -806,7 +813,7 @@ ecore_dmae_execute_command(struct ecore_hwfn *p_hwfn,
u8 src_type,
u8 dst_type,
u32 size_in_dwords,
- struct ecore_dmae_params *p_params)
+ struct dmae_params *p_params)
{
dma_addr_t phys = p_hwfn->dmae_info.completion_word_phys_addr;
u16 length_cur = 0, i = 0, cnt_split = 0, length_mod = 0;
@@ -910,7 +917,7 @@ enum _ecore_status_t ecore_dmae_host2grc(struct ecore_hwfn *p_hwfn,
u64 source_addr,
u32 grc_addr,
u32 size_in_dwords,
- struct ecore_dmae_params *p_params)
+ struct dmae_params *p_params)
{
u32 grc_addr_in_dw = grc_addr / sizeof(u32);
enum _ecore_status_t rc;
@@ -933,7 +940,7 @@ enum _ecore_status_t ecore_dmae_grc2host(struct ecore_hwfn *p_hwfn,
u32 grc_addr,
dma_addr_t dest_addr,
u32 size_in_dwords,
- struct ecore_dmae_params *p_params)
+ struct dmae_params *p_params)
{
u32 grc_addr_in_dw = grc_addr / sizeof(u32);
enum _ecore_status_t rc;
@@ -955,7 +962,8 @@ ecore_dmae_host2host(struct ecore_hwfn *p_hwfn,
struct ecore_ptt *p_ptt,
dma_addr_t source_addr,
dma_addr_t dest_addr,
- u32 size_in_dwords, struct ecore_dmae_params *p_params)
+ u32 size_in_dwords,
+ struct dmae_params *p_params)
{
enum _ecore_status_t rc;
diff --git a/drivers/net/qede/base/ecore_hw.h b/drivers/net/qede/base/ecore_hw.h
index 0b5b40c46..e43f337dc 100644
--- a/drivers/net/qede/base/ecore_hw.h
+++ b/drivers/net/qede/base/ecore_hw.h
@@ -31,23 +31,7 @@ enum reserved_ptts {
#define MISC_REG_DRIVER_CONTROL_0_SIZE MISC_REG_DRIVER_CONTROL_1_SIZE
#endif
-enum _dmae_cmd_dst_mask {
- DMAE_CMD_DST_MASK_NONE = 0,
- DMAE_CMD_DST_MASK_PCIE = 1,
- DMAE_CMD_DST_MASK_GRC = 2
-};
-
-enum _dmae_cmd_src_mask {
- DMAE_CMD_SRC_MASK_PCIE = 0,
- DMAE_CMD_SRC_MASK_GRC = 1
-};
-
-enum _dmae_cmd_crc_mask {
- DMAE_CMD_COMP_CRC_EN_MASK_NONE = 0,
- DMAE_CMD_COMP_CRC_EN_MASK_SET = 1
-};
-
-/* definitions for DMA constants */
+/* Definitions for DMA constants */
#define DMAE_GO_VALUE 0x1
#ifdef __BIG_ENDIAN
@@ -258,16 +242,78 @@ enum _ecore_status_t ecore_dmae_info_alloc(struct ecore_hwfn *p_hwfn);
*/
void ecore_dmae_info_free(struct ecore_hwfn *p_hwfn);
-enum _ecore_status_t ecore_init_fw_data(struct ecore_dev *p_dev,
- const u8 *fw_data);
+/**
+ * @brief ecore_dmae_host2grc - copy data from source address to
+ * dmae registers using the given ptt
+ *
+ * @param p_hwfn
+ * @param p_ptt
+ * @param source_addr
+ * @param grc_addr (dmae_data_offset)
+ * @param size_in_dwords
+ * @param p_params (default parameters will be used in case of OSAL_NULL)
+ *
+ * @return enum _ecore_status_t
+ */
+enum _ecore_status_t
+ecore_dmae_host2grc(struct ecore_hwfn *p_hwfn,
+ struct ecore_ptt *p_ptt,
+ u64 source_addr,
+ u32 grc_addr,
+ u32 size_in_dwords,
+ struct dmae_params *p_params);
-void ecore_hw_err_notify(struct ecore_hwfn *p_hwfn,
- enum ecore_hw_err_type err_type);
+/**
+ * @brief ecore_dmae_grc2host - Read data from dmae data offset
+ * to source address using the given ptt
+ *
+ * @param p_ptt
+ * @param grc_addr (dmae_data_offset)
+ * @param dest_addr
+ * @param size_in_dwords
+ * @param p_params (default parameters will be used in case of OSAL_NULL)
+ *
+ * @return enum _ecore_status_t
+ */
+enum _ecore_status_t
+ecore_dmae_grc2host(struct ecore_hwfn *p_hwfn,
+ struct ecore_ptt *p_ptt,
+ u32 grc_addr,
+ dma_addr_t dest_addr,
+ u32 size_in_dwords,
+ struct dmae_params *p_params);
+
+/**
+ * @brief ecore_dmae_host2host - copy data from to source address
+ * to a destination address (for SRIOV) using the given ptt
+ *
+ * @param p_hwfn
+ * @param p_ptt
+ * @param source_addr
+ * @param dest_addr
+ * @param size_in_dwords
+ * @param p_params (default parameters will be used in case of OSAL_NULL)
+ *
+ * @return enum _ecore_status_t
+ */
+enum _ecore_status_t
+ecore_dmae_host2host(struct ecore_hwfn *p_hwfn,
+ struct ecore_ptt *p_ptt,
+ dma_addr_t source_addr,
+ dma_addr_t dest_addr,
+ u32 size_in_dwords,
+ struct dmae_params *p_params);
enum _ecore_status_t ecore_dmae_sanity(struct ecore_hwfn *p_hwfn,
struct ecore_ptt *p_ptt,
const char *phase);
+enum _ecore_status_t ecore_init_fw_data(struct ecore_dev *p_dev,
+ const u8 *fw_data);
+
+void ecore_hw_err_notify(struct ecore_hwfn *p_hwfn,
+ enum ecore_hw_err_type err_type);
+
/**
* @brief ecore_ppfid_wr - Write value to BAR using the given ptt while
* pretending to a PF to which the given PPFID pertains.
diff --git a/drivers/net/qede/base/ecore_init_ops.c b/drivers/net/qede/base/ecore_init_ops.c
index 044308bf4..8f7209100 100644
--- a/drivers/net/qede/base/ecore_init_ops.c
+++ b/drivers/net/qede/base/ecore_init_ops.c
@@ -179,12 +179,12 @@ static enum _ecore_status_t ecore_init_fill_dmae(struct ecore_hwfn *p_hwfn,
u32 addr, u32 fill_count)
{
static u32 zero_buffer[DMAE_MAX_RW_SIZE];
- struct ecore_dmae_params params;
+ struct dmae_params params;
OSAL_MEMSET(zero_buffer, 0, sizeof(u32) * DMAE_MAX_RW_SIZE);
OSAL_MEMSET(¶ms, 0, sizeof(params));
- params.flags = ECORE_DMAE_FLAG_RW_REPL_SRC;
+ SET_FIELD(params.flags, DMAE_PARAMS_RW_REPL_SRC, 0x1);
return ecore_dmae_host2grc(p_hwfn, p_ptt,
(osal_uintptr_t)&zero_buffer[0],
addr, fill_count, ¶ms);
diff --git a/drivers/net/qede/base/ecore_sriov.c b/drivers/net/qede/base/ecore_sriov.c
index d771ac6d4..264217252 100644
--- a/drivers/net/qede/base/ecore_sriov.c
+++ b/drivers/net/qede/base/ecore_sriov.c
@@ -347,7 +347,7 @@ enum _ecore_status_t ecore_iov_post_vf_bulletin(struct ecore_hwfn *p_hwfn,
{
struct ecore_bulletin_content *p_bulletin;
int crc_size = sizeof(p_bulletin->crc);
- struct ecore_dmae_params params;
+ struct dmae_params params;
struct ecore_vf_info *p_vf;
p_vf = ecore_iov_get_vf_info(p_hwfn, (u16)vfid, true);
@@ -371,8 +371,8 @@ enum _ecore_status_t ecore_iov_post_vf_bulletin(struct ecore_hwfn *p_hwfn,
/* propagate bulletin board via dmae to vm memory */
OSAL_MEMSET(¶ms, 0, sizeof(params));
- params.flags = ECORE_DMAE_FLAG_VF_DST;
- params.dst_vfid = p_vf->abs_vf_id;
+ SET_FIELD(params.flags, DMAE_PARAMS_DST_VF_VALID, 0x1);
+ params.dst_vf_id = p_vf->abs_vf_id;
return ecore_dmae_host2host(p_hwfn, p_ptt, p_vf->bulletin.phys,
p_vf->vf_bulletin, p_vf->bulletin.size / 4,
¶ms);
@@ -1374,7 +1374,7 @@ static void ecore_iov_send_response(struct ecore_hwfn *p_hwfn,
u8 status)
{
struct ecore_iov_vf_mbx *mbx = &p_vf->vf_mbx;
- struct ecore_dmae_params params;
+ struct dmae_params params;
u8 eng_vf_id;
mbx->reply_virt->default_resp.hdr.status = status;
@@ -1391,9 +1391,9 @@ static void ecore_iov_send_response(struct ecore_hwfn *p_hwfn,
eng_vf_id = p_vf->abs_vf_id;
- OSAL_MEMSET(¶ms, 0, sizeof(struct ecore_dmae_params));
- params.flags = ECORE_DMAE_FLAG_VF_DST;
- params.dst_vfid = eng_vf_id;
+ OSAL_MEMSET(¶ms, 0, sizeof(struct dmae_params));
+ SET_FIELD(params.flags, DMAE_PARAMS_DST_VF_VALID, 0x1);
+ params.dst_vf_id = eng_vf_id;
ecore_dmae_host2host(p_hwfn, p_ptt, mbx->reply_phys + sizeof(u64),
mbx->req_virt->first_tlv.reply_address +
@@ -4389,16 +4389,17 @@ u16 ecore_iov_get_next_active_vf(struct ecore_hwfn *p_hwfn, u16 rel_vf_id)
enum _ecore_status_t ecore_iov_copy_vf_msg(struct ecore_hwfn *p_hwfn,
struct ecore_ptt *ptt, int vfid)
{
- struct ecore_dmae_params params;
+ struct dmae_params params;
struct ecore_vf_info *vf_info;
vf_info = ecore_iov_get_vf_info(p_hwfn, (u16)vfid, true);
if (!vf_info)
return ECORE_INVAL;
- OSAL_MEMSET(¶ms, 0, sizeof(struct ecore_dmae_params));
- params.flags = ECORE_DMAE_FLAG_VF_SRC | ECORE_DMAE_FLAG_COMPLETION_DST;
- params.src_vfid = vf_info->abs_vf_id;
+ OSAL_MEMSET(¶ms, 0, sizeof(struct dmae_params));
+ SET_FIELD(params.flags, DMAE_PARAMS_SRC_VF_VALID, 0x1);
+ SET_FIELD(params.flags, DMAE_PARAMS_COMPLETION_DST, 0x1);
+ params.src_vf_id = vf_info->abs_vf_id;
if (ecore_dmae_host2host(p_hwfn, ptt,
vf_info->vf_mbx.pending_req,
--
2.18.0
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