[dpdk-dev] [EXT] Re: [PATCH v2 1/2] ethdev: add level support for RSS offload types

Kiran Kumar Kokkilagadda kirankumark at marvell.com
Fri Aug 14 05:55:15 CEST 2020



From: Ajit Khaparde <ajit.khaparde at broadcom.com>
Sent: Saturday, August 8, 2020 8:10 PM
To: Kiran Kumar Kokkilagadda <kirankumark at marvell.com>
Cc: Andrew Rybchenko <arybchenko at solarflare.com>; Ferruh Yigit <ferruh.yigit at intel.com>; Thomas Monjalon <thomas at monjalon.net>; beilei.xing at intel.com; chas3 at att.com; cloud.wangxiaoyun at huawei.com; cristian.dumitrescu at intel.com; dev at dpdk.org; grive at u256.net; hemant.agrawal at nxp.com; humin29 at huawei.com; hyonkim at cisco.com; jasvinder.singh at intel.com; Jerin Jacob Kollanukkaran <jerinj at marvell.com>; jia.guo at intel.com; jingjing.wu at intel.com; johndale at cisco.com; keith.wiles at intel.com; Liron Himi <lironh at marvell.com>; matan at mellanox.com; Nithin Kumar Dabilpuram <ndabilpuram at marvell.com>; orika at mellanox.com; qi.z.zhang at intel.com; qiming.yang at intel.com; rahul.lakkireddy at chelsio.com; Rasesh Mody <rmody at marvell.com>; rosen.xu at intel.com; sachin.saxena at nxp.com; shahafs at mellanox.com; Shahed Shaikh <shshaikh at marvell.com>; somnath.kotur at broadcom.com; viacheslavo at mellanox.com; wei.zhao1 at intel.com; xavier.huwei at huawei.com; xuanziyang2 at huawei.com; yisen.zhuang at huawei.com; zhouguoyang at huawei.com
Subject: [EXT] Re: [dpdk-dev][PATCH v2 1/2] ethdev: add level support for RSS offload types

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On Sat, Aug 8, 2020 at 7:36 AM <kirankumark at marvell.com<mailto:kirankumark at marvell.com>> wrote:
From: Kiran Kumar K <kirankumark at marvell.com<mailto:kirankumark at marvell.com>>

This patch reserves 2 bits as input selection to select Inner and
outer layers for RSS computation. It is combined with existing
ETH_RSS_* to choose Inner or outer layers for L2, L3 and L4.
How do you plan to use this? Do you need to make any changes to testpmd?

I will update in the next version.


This functionality already exists in rte_flow through level parameter in
RSS action configuration rte_flow_action_rss.

Signed-off-by: Kiran Kumar K <kirankumark at marvell.com<mailto:kirankumark at marvell.com>>
---
v2 changes:
* Reserved bit 50 & 51

 lib/librte_ethdev/rte_ethdev.h | 27 +++++++++++++++++++++++++++
 1 file changed, 27 insertions(+)

diff --git a/lib/librte_ethdev/rte_ethdev.h b/lib/librte_ethdev/rte_ethdev.h
index d29930fd8..28184cc85 100644
--- a/lib/librte_ethdev/rte_ethdev.h
+++ b/lib/librte_ethdev/rte_ethdev.h
@@ -552,6 +552,33 @@ struct rte_eth_rss_conf {
 #define RTE_ETH_RSS_L3_PRE64      (1ULL << 53)
 #define RTE_ETH_RSS_L3_PRE96      (1ULL << 52)

+/*
+ * We use the following macros to combine with the above layers to choose
+ * inner and outer layers or both for RSS computation.
+ * Note: Default is 0: inner layers, 1: outer layers, 2: both
+ * bit 50 and 51 are reserved for this.
+ */
+
+/**
+ * Level 0, It basically stands for the innermost encapsulation level RSS
+ * can be performed on according to PMD and device capabilities.
+ */
+#define ETH_RSS_LEVEL_INNER        (0ULL << 50)
+/**
+ * Level 1, It basically stands for the outermost encapsulation level RSS
+ * can be performed on according to PMD and device capabilities.
+ */
+#define ETH_RSS_LEVEL_OUTER        (1ULL << 50)
+/**
+ * Level 2, It basically stands for the both inner and outermost
+ * encapsulation level RSS can be performed on according to PMD and
+ * device capabilities.
+ */
+#define ETH_RSS_LEVEL_INNER_OUTER  (2ULL << 50)
+#define ETH_RSS_LEVEL_MASK        (3ULL << 50)
+
+#define ETH_RSS_LEVEL(rss_hf) ((rss_hf & ETH_RSS_LEVEL_MASK) >> 50)
+
 /**
  * For input set change of hash filter, if SRC_ONLY and DST_ONLY of
  * the same level are used simultaneously, it is the same case as
--
2.25.1


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