[dpdk-dev] [PATCH v2 17/17] net: add checks for max SIMD bitwidth

[Ciara Power]

When choosing a vector path to take, an extra condition must be
satisfied to ensure the max SIMD bitwidth allows for the CPU enabled
path. This check is done just before the handler is called, it cannot
be done when setting the handlers initially as the EAL max simd bitwidth
value has not yet been set.

Cc: Jasvinder Singh <jasvinder.singh at intel.com>

Signed-off-by: Ciara Power <ciara.power at intel.com>
---
 lib/librte_net/rte_net_crc.c | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/lib/librte_net/rte_net_crc.c b/lib/librte_net/rte_net_crc.c
index 9fd4794a9d..d3d3206919 100644
--- a/lib/librte_net/rte_net_crc.c
+++ b/lib/librte_net/rte_net_crc.c
@@ -9,6 +9,7 @@
 #include <rte_cpuflags.h>
 #include <rte_common.h>
 #include <rte_net_crc.h>
+#include <rte_eal.h>
 
 #if defined(RTE_ARCH_X86_64) && defined(RTE_MACHINE_CPUFLAG_PCLMULQDQ)
 #define X86_64_SSE42_PCLMULQDQ     1
@@ -60,6 +61,8 @@ static rte_net_crc_handler handlers_neon[] = {
 };
 #endif
 
+static uint16_t max_simd_bitwidth;
+
 /**
  * Reflect the bits about the middle
  *
@@ -175,6 +178,11 @@ rte_net_crc_calc(const void *data,
 	uint32_t ret;
 	rte_net_crc_handler f_handle;
 
+	if (max_simd_bitwidth == 0)
+		max_simd_bitwidth = rte_get_max_simd_bitwidth();
+	if (max_simd_bitwidth < RTE_MAX_128_SIMD &&
+			handlers != handlers_scalar)
+		rte_net_crc_set_alg(RTE_NET_CRC_SCALAR);
 	f_handle = handlers[type];
 	ret = f_handle(data, data_len);
 
-- 
2.17.1