[dpdk-dev] [PATCH v2] mempool/octeontx2: optimize for L1D cache architecture

[Jerin Jacob]

On Fri, Jan 31, 2020 at 10:53 PM <pbhagavatula at marvell.com> wrote:
>
> From: Pavan Nikhilesh <pbhagavatula at marvell.com>
>
> OCTEON TX2 has 8 sets, 41 ways L1D cache, VA<9:7> bits dictate
> the set selection.
> Add additional padding to ensure that the element size always
> occupies odd number of cachelines to ensure even distribution
> of elements among L1D cache sets.
>
> Signed-off-by: Pavan Nikhilesh <pbhagavatula at marvell.com>
> Signed-off-by: Nithin Dabilpuram <ndabilpuram at marvell.com>
> Signed-off-by: Vamsi Attunuru <vattunuru at marvell.com>
> Signed-off-by: Jerin Jacob <jerinj at marvell.com>
> ---
>  v2 Changes:
>  ----------
>  - Fix 32bit build break.


Acked-by: Jerin Jacob <jerinj at marvell.com>

Delegated the patch to Thomas as it has come through the main tree.