[dpdk-dev] [EXT] Re: [PATCH v3 1/6] drivers: add generic API to find PCI extended cap

Xu, Rosen rosen.xu at intel.com
Mon Jul 27 09:32:53 CEST 2020


Hi,

> -----Original Message-----
> From: Manish Chopra <manishc at marvell.com>
> Sent: Monday, July 27, 2020 13:11
> To: Gaëtan Rivet <grive at u256.net>
> Cc: jerinjacobk at gmail.com; Jerin Jacob Kollanukkaran <jerinj at marvell.com>;
> Yigit, Ferruh <ferruh.yigit at intel.com>; dev at dpdk.org; Igor Russkikh
> <irusskikh at marvell.com>; Rasesh Mody <rmody at marvell.com>; GR-
> Everest-DPDK-Dev <GR-Everest-DPDK-Dev at marvell.com>; Xu, Rosen
> <rosen.xu at intel.com>; Zhang, Tianfei <tianfei.zhang at intel.com>;
> heinrich.kuhn at netronome.com; Yang, Qiming <qiming.yang at intel.com>;
> Zhang, Qi Z <qi.z.zhang at intel.com>
> Subject: RE: [EXT] Re: [PATCH v3 1/6] drivers: add generic API to find PCI
> extended cap
> 
> > -----Original Message-----
> > From: Gaëtan Rivet <grive at u256.net>
> > Sent: Monday, July 27, 2020 4:18 AM
> > To: Manish Chopra <manishc at marvell.com>
> > Cc: jerinjacobk at gmail.com; Jerin Jacob Kollanukkaran
> > <jerinj at marvell.com>; ferruh.yigit at intel.com; dev at dpdk.org; Igor
> > Russkikh <irusskikh at marvell.com>; Rasesh Mody <rmody at marvell.com>;
> > GR-Everest- DPDK-Dev <GR-Everest-DPDK-Dev at marvell.com>;
> > rosen.xu at intel.com; tianfei.zhang at intel.com;
> > heinrich.kuhn at netronome.com; qiming.yang at intel.com;
> > qi.z.zhang at intel.com
> > Subject: Re: [EXT] Re: [PATCH v3 1/6] drivers: add generic API to find
> > PCI extended cap
> >
> > On 26/07/20 19:47 +0000, Manish Chopra wrote:
> >
> > [...]
> >
> > > > > diff --git a/lib/librte_pci/rte_pci.h b/lib/librte_pci/rte_pci.h
> > > > > index a03235da1..fec51e15a 100644
> > > > > --- a/lib/librte_pci/rte_pci.h
> > > > > +++ b/lib/librte_pci/rte_pci.h
> > > > > @@ -22,6 +22,22 @@ extern "C" {
> > > > >  #include <inttypes.h>
> > > > >  #include <sys/types.h>
> > > > >
> > > > > +
> > > > > +/*
> > > > > + * Conventional PCI and PCI-X Mode 1 devices have 256 bytes of
> > > > > + * configuration space.  PCI-X Mode 2 and PCIe devices have
> > > > > +4096 bytes of
> > > > > + * configuration space.
> > > > > + */
> > > > > +#define RTE_PCI_CFG_SPACE_SIZE		256
> > > > > +#define RTE_PCI_CFG_SPACE_EXP_SIZE	4096
> > > > > +
> > > > > +/* Extended Capabilities (PCI-X 2.0 and Express) */
> > > > > +#define RTE_PCI_EXT_CAP_ID(header)	(header & 0x0000ffff)
> > > > > +#define RTE_PCI_EXT_CAP_NEXT(header)	((header >> 20) &
> > 0xffc)
> > > > > +
> > > > > +#define RTE_PCI_EXT_CAP_ID_ERR	0x01	/* Advanced Error
> > Reporting
> > > > */
> > > > > +#define RTE_PCI_EXT_CAP_ID_DSN	0x03	/* Device Serial
> > Number */
> > > > > +
> > > >
> > > > I understand that it is more natural to have those defines in the
> > > > PCI lib, but I think there is no point in adding them in a
> > > > separate lib, while the function using those is in the PCI bus.
> > > >
> > > > I think the defines should be put right before the
> > > > rte_pci_find_next_ext_capability() prototype in
> > > > drivers/bus/pci/rte_bus_pci.h.
> > >
> > > Hello Gaetan,
> > >
> > > I think these comes in the category of all RTE_PCI_* generic defines
> > > (not just use in drivers/bus/pci/), Since caller of the API also
> > > need to use it, For example, couple of RTE_PCI_* were added in patch
> > > #2 used by qede drivers specifically. rte_pci.h sounds more generic
> > > than
> > rte_bus_pci.h hence I thought it is the suitable place to consolidate
> > them in there.
> > >
> > > Thanks !!
> >
> > Reading the additional symbols, particularly about SRIOV capa, I think
> > you are right, it's probably better to have it all within rte_pci.h.
> >
> > To help developers, it would be better to point in the doc that the
> > capability IDs useable as parameter `cap` can be any from
> > RTE_PCI_EXT_CAP_ID_*, defined within librte_pci. The dev can then grep it.
> 
> Sure, I will add the pointer to librte_pci in the comment section for
> rte_pci_find_next_ext_capability()
> 
> >
> > One additional thing:
> >
> > > > > +#define RTE_PCI_CFG_SPACE_SIZE		256
> > > > > +#define RTE_PCI_CFG_SPACE_EXP_SIZE	4096
> > > > > +
> > > > > +/* Extended Capabilities (PCI-X 2.0 and Express) */
> > > > > +#define RTE_PCI_EXT_CAP_ID(header)	(header & 0x0000ffff)
> > > > > +#define RTE_PCI_EXT_CAP_NEXT(header)	((header >> 20) &
> > 0xffc)
> >
> > I think those macros are not useful as part of the public API, they
> > are only used to implement rte_pci_find_next_ext_capability(). Can you
> > confirm? If this is correct, I think they should be moved to the
> > compilation unit implementing rte_pci_find_next_ext_capability().
> >
> 
> Hi Gaetan,
> 
> Yes Mostly, but there is a similar piece of code left in drivers/raw/ifpga
> [ifpga_pci_find_ext_capability()] only which utilizes these symbols as well,
> which I did not want to be removed/cleaned up must as a part of this series
> because that implementation is based on pread() instead of
> rte_pci_read_config(). I was not sure if that driver can also directly use
> rte_pci_find_next_ext_capability() too, I do not have those fpga based
> devices to test if at all I were to do that cleanup/removal now in that driver,
> so I didn't attempt to make such functional changes in that driver now. [May
> be this can be cleaned up too later on with proper testing or may be a new
> API based on pread() can be added further if those drivers can't use
> rte_pci_find_next_ext_capability() directly].

For drivers/raw/ifpga is using these macros, I prefer to keep it.

> Thanks.


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