[dpdk-dev] [PATCH v6] eal/arm64: fix rdtsc precise version
Linhaifeng
haifeng.lin at huawei.com
Wed Mar 11 08:24:10 CET 2020
In order to get more accurate the cntvct_el0 reading,
SW must invoke isb and arch_counter_enforce_ordering.
Reference of linux kernel:
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/
linux.git/tree/arch/arm64/include/asm/arch_timer.h?h=v5.5#n220
Fixes: ccad39ea0712 ("eal/arm: add cpu cycle operations for ARMv8")
Cc: stable at dpdk.org
Reviewed-by: Jerin Jacob <jerinjacobk at gmail.com>
Reviewed-by: Gavin Hu <gavin.hu at arm.com>
Signed-off-by: Haifeng Lin <haifeng.lin at huawei.com>
---
.../common/include/arch/arm/rte_cycles_64.h | 26 +++++++++++++++++--
1 file changed, 24 insertions(+), 2 deletions(-)
diff --git a/lib/librte_eal/common/include/arch/arm/rte_cycles_64.h b/lib/librte_eal/common/include/arch/arm/rte_cycles_64.h
index 68e7c7338..6b0df5b0a 100644
--- a/lib/librte_eal/common/include/arch/arm/rte_cycles_64.h
+++ b/lib/librte_eal/common/include/arch/arm/rte_cycles_64.h
@@ -59,11 +59,33 @@ rte_rdtsc(void)
}
#endif
+static inline void
+isb(void)
+{
+ asm volatile("isb" : : : "memory");
+}
+
+static inline void
+__rte_arm64_cntvct_el0_enforce_ordering(uint64_t val)
+{
+ uint64_t tmp;
+
+ asm volatile(
+ " eor %0, %1, %1\n"
+ " add %0, sp, %0\n"
+ " ldr xzr, [%0]"
+ : "=r" (tmp) : "r" (val));
+}
+
static inline uint64_t
rte_rdtsc_precise(void)
{
- rte_mb();
- return rte_rdtsc();
+ uint64_t tsc;
+
+ isb();
+ tsc = rte_rdtsc();
+ __rte_arm64_cntvct_el0_enforce_ordering(tsc);
+ return tsc;
}
static inline uint64_t
--
2.24.1.windows.2
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