[dpdk-dev] [PATCH] net/mlx5: fix the eCPRI common header endianness

[Raslan Darawsheh]

Hi,
> -----Original Message-----
> From: Bing Zhao <bingz at nvidia.com>
> Sent: Tuesday, November 3, 2020 7:42 AM
> To: Slava Ovsiienko <viacheslavo at nvidia.com>; Matan Azrad
> <matan at nvidia.com>
> Cc: dev at dpdk.org; Ori Kam <orika at nvidia.com>; Raslan Darawsheh
> <rasland at nvidia.com>; stable at dpdk.org
> Subject: [PATCH] net/mlx5: fix the eCPRI common header endianness
> 
> The input header of a RTE flow item is with network byte order. In
> the host with little endian, the bit field order are the same as the
> byte order.
> When checking the an eCPRI message type, the wrong field will be
> selected. Right now, since the whole u32 is being checked and for
> all types, the following implementation is unique. There is no
> functional risk but it is still an error to fix.
> 
> Fixes: daa38a8924a0 ("net/mlx5: add flow translation of eCPRI header")
> 
> Cc: stable at dpdk.org
> 
> Signed-off-by: Bing Zhao <bingz at nvidia.com>
> Acked-by: Viacheslav Ovsiienko <viacheslavo at nvidia.com>
> ---
>  drivers/net/mlx5/mlx5_flow_dv.c | 4 +++-
>  1 file changed, 3 insertions(+), 1 deletion(-)
> 
Patch applied to next-net-mlx,

Kindest regards,
Raslan Darawsheh