[dpdk-dev] [PATCH] net/mlx5: fix DevX CQ attributes values
Raslan Darawsheh
rasland at nvidia.com
Thu Oct 1 10:41:35 CEST 2020
Hi,
> -----Original Message-----
> From: dev <dev-bounces at dpdk.org> On Behalf Of Dekel Peled
> Sent: Wednesday, September 30, 2020 3:20 PM
> To: Slava Ovsiienko <viacheslavo at nvidia.com>; Shahaf Shuler
> <shahafs at nvidia.com>; Matan Azrad <matan at nvidia.com>
> Cc: dev at dpdk.org; stable at dpdk.org
> Subject: [dpdk-dev] [PATCH] net/mlx5: fix DevX CQ attributes values
>
> Previous patch wrongly used rdma-core defined values, when preparing
> attributes for creating DevX CQ object.
> This patch adds the correct value definition and uses them instead.
>
> Fixes: 08d1838f645a ("net/mlx5: implement CQ for Rx using DevX API")
> Cc: stable at dpdk.org
>
> Signed-off-by: Dekel Peled <dekelp at nvidia.com>
> Acked-by: Matan Azrad <matan at nvidia.com>
> ---
> drivers/common/mlx5/mlx5_prm.h | 8 ++++++++
> drivers/net/mlx5/mlx5_devx.c | 14 ++++----------
> 2 files changed, 12 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/common/mlx5/mlx5_prm.h
> b/drivers/common/mlx5/mlx5_prm.h
> index 563e7c8..20f2fcc 100644
> --- a/drivers/common/mlx5/mlx5_prm.h
> +++ b/drivers/common/mlx5/mlx5_prm.h
> @@ -2835,6 +2835,14 @@ struct mlx5_mini_cqe8 {
> uint32_t byte_cnt;
> };
>
> +/* Mini CQE responder format. */
> +enum {
> + MLX5_CQE_RESP_FORMAT_HASH = 0x0,
> + MLX5_CQE_RESP_FORMAT_CSUM = 0x1,
> + MLX5_CQE_RESP_FORMAT_CSUM_FLOW_TAG = 0x2,
> + MLX5_CQE_RESP_FORMAT_CSUM_STRIDX = 0x3,
> +};
> +
> /* srTCM PRM flow meter parameters. */
> enum {
> MLX5_FLOW_COLOR_RED = 0,
> diff --git a/drivers/net/mlx5/mlx5_devx.c b/drivers/net/mlx5/mlx5_devx.c
> index 3e81fcc..cb4a522 100644
> --- a/drivers/net/mlx5/mlx5_devx.c
> +++ b/drivers/net/mlx5/mlx5_devx.c
> @@ -367,15 +367,11 @@
> }
> if (priv->config.cqe_comp && !rxq_data->hw_timestamp &&
> !rxq_data->lro) {
> - cq_attr.cqe_comp_en =
> MLX5DV_CQ_INIT_ATTR_MASK_COMPRESSED_CQE;
> -#ifdef HAVE_IBV_DEVICE_STRIDING_RQ_SUPPORT
> + cq_attr.cqe_comp_en = 1u;
> cq_attr.mini_cqe_res_format =
> mlx5_rxq_mprq_enabled(rxq_data) ?
> - MLX5DV_CQE_RES_FORMAT_CSUM_STRIDX
> :
> - MLX5DV_CQE_RES_FORMAT_HASH;
> -#else
> - cq_attr.mini_cqe_res_format =
> MLX5DV_CQE_RES_FORMAT_HASH;
> -#endif
> +
> MLX5_CQE_RESP_FORMAT_CSUM_STRIDX :
> + MLX5_CQE_RESP_FORMAT_HASH;
> /*
> * For vectorized Rx, it must not be doubled in order to
> * make cq_ci and rq_ci aligned.
> @@ -392,10 +388,8 @@
> "Port %u Rx CQE compression is disabled for LRO.",
> dev->data->port_id);
> }
> -#ifdef HAVE_IBV_MLX5_MOD_CQE_128B_PAD
> if (priv->config.cqe_pad)
> - cq_attr.cqe_size =
> MLX5DV_CQ_INIT_ATTR_FLAGS_CQE_PAD;
> -#endif
> + cq_attr.cqe_size = MLX5_CQE_SIZE_128B;
> log_cqe_n = log2above(cqe_n);
> cq_size = sizeof(struct mlx5_cqe) * (1 << log_cqe_n);
> /* Query the EQN for this core. */
> --
> 1.8.3.1
Patch applied to next-net-mlx,
Kindest regards,
Raslan Darawsheh
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