[dpdk-dev] [PATCH v3 09/15] net/i40e/base: enable pipe monitor thresholds

[Guinan Sun]

Enable several registers and defines for software controlled
DCB, particularly around the receive pipe monitor configuration
which is necessary to help ports achieve the right throughput
under load in several different configurations.

Signed-off-by: Jesse Brandeburg <jesse.brandeburg at intel.com>
Signed-off-by: Guinan Sun <guinanx.sun at intel.com>
---
 drivers/net/i40e/base/i40e_register.h | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/net/i40e/base/i40e_register.h b/drivers/net/i40e/base/i40e_register.h
index ee4f333f9..ee443e9c9 100644
--- a/drivers/net/i40e/base/i40e_register.h
+++ b/drivers/net/i40e/base/i40e_register.h
@@ -203,6 +203,9 @@
 #define I40E_VFCM_PE_ERRINFO1_RLU_ERROR_CNT_MASK  I40E_MASK(0xFF, I40E_VFCM_PE_ERRINFO1_RLU_ERROR_CNT_SHIFT)
 #define I40E_VFCM_PE_ERRINFO1_RLS_ERROR_CNT_SHIFT 24
 #define I40E_VFCM_PE_ERRINFO1_RLS_ERROR_CNT_MASK  I40E_MASK(0xFF, I40E_VFCM_PE_ERRINFO1_RLS_ERROR_CNT_SHIFT)
+#define I40E_PRT_SWR_PM_THR                 0x0026CD00 /* Reset: CORER */
+#define I40E_PRT_SWR_PM_THR_THRESHOLD_SHIFT 0
+#define I40E_PRT_SWR_PM_THR_THRESHOLD_MASK  I40E_MASK(0xFF, I40E_PRT_SWR_PM_THR_THRESHOLD_SHIFT)
 #define I40E_GLDCB_GENC              0x00083044 /* Reset: CORER */
 #define I40E_GLDCB_GENC_PCIRTT_SHIFT 0
 #define I40E_GLDCB_GENC_PCIRTT_MASK  I40E_MASK(0xFFFF, I40E_GLDCB_GENC_PCIRTT_SHIFT)
-- 
2.17.1