[dpdk-dev] [PATCH v16 4/8] eal/arm: update CPU flags

[Juraj Linkeš]

Addining Jerin, Jan and Ruifeng

> -----Original Message-----
> From: Juraj Linkeš <juraj.linkes at pantheon.tech>
> Sent: Wednesday, April 21, 2021 10:50 AM
> To: thomas at monjalon.net; david.marchand at redhat.com;
> bruce.richardson at intel.com; aconole at redhat.com;
> maicolgabriel at hotmail.com
> Cc: Juraj Linkeš <juraj.linkes at pantheon.tech>; dev at dpdk.org
> Subject: [PATCH v16 4/8] eal/arm: update CPU flags
> 
> There are two execution states on armv8 architecture, aarch64 and aarch32.
> Add PLATFORM_STR for the latter and update RTE_ARCH_* flags according to
> e9b97392640.
> 
> Signed-off-by: Juraj Linkeš <juraj.linkes at pantheon.tech>
> ---
>  lib/librte_eal/arm/include/rte_cpuflags_32.h | 1 +
>  lib/librte_eal/arm/rte_cpuflags.c            | 9 +++++++--
>  2 files changed, 8 insertions(+), 2 deletions(-)
> 
> diff --git a/lib/librte_eal/arm/include/rte_cpuflags_32.h
> b/lib/librte_eal/arm/include/rte_cpuflags_32.h
> index b5347be1ec..4e254428a2 100644
> --- a/lib/librte_eal/arm/include/rte_cpuflags_32.h
> +++ b/lib/librte_eal/arm/include/rte_cpuflags_32.h
> @@ -41,6 +41,7 @@ enum rte_cpu_flag_t {
>  	RTE_CPUFLAG_SHA2,
>  	RTE_CPUFLAG_CRC32,
>  	RTE_CPUFLAG_V7L,
> +	RTE_CPUFLAG_V8L,
>  	/* The last item */
>  	RTE_CPUFLAG_NUMFLAGS,/**< This should always be the last! */  };
> diff --git a/lib/librte_eal/arm/rte_cpuflags.c b/lib/librte_eal/arm/rte_cpuflags.c
> index e3a53bcece..4167a1a302 100644
> --- a/lib/librte_eal/arm/rte_cpuflags.c
> +++ b/lib/librte_eal/arm/rte_cpuflags.c
> @@ -46,8 +46,12 @@ struct feature_entry {  #define FEAT_DEF(name, reg, bit) \
>  	[RTE_CPUFLAG_##name] = {reg, bit, #name},
> 
> +#ifdef RTE_ARCH_32
>  #ifdef RTE_ARCH_ARMv7
>  #define PLATFORM_STR "v7l"
> +#elif defined RTE_ARCH_ARMv8_AARCH32
> +#define PLATFORM_STR "v8l"
> +#endif
>  typedef Elf32_auxv_t _Elfx_auxv_t;
> 
>  const struct feature_entry rte_cpu_feature_table[] = { @@ -79,9 +83,10 @@
> const struct feature_entry rte_cpu_feature_table[] = {
>  	FEAT_DEF(SHA2,      REG_HWCAP2,   3)
>  	FEAT_DEF(CRC32,     REG_HWCAP2,   4)
>  	FEAT_DEF(V7L,       REG_PLATFORM, 0)
> +	FEAT_DEF(V8L,       REG_PLATFORM, 0)
>  };
> 
> -#elif defined RTE_ARCH_ARM64
> +#elif defined RTE_ARCH_64
>  #define PLATFORM_STR "aarch64"
>  typedef Elf64_auxv_t _Elfx_auxv_t;
> 
> @@ -108,7 +113,7 @@ const struct feature_entry rte_cpu_feature_table[] = {
>  	FEAT_DEF(SVEF32MM,	REG_HWCAP2,   10)
>  	FEAT_DEF(SVEF64MM,	REG_HWCAP2,   11)
>  	FEAT_DEF(SVEBF16,	REG_HWCAP2,   12)
> -	FEAT_DEF(AARCH64,	REG_PLATFORM, 1)
> +	FEAT_DEF(AARCH64,	REG_PLATFORM, 0)
>  };
>  #endif /* RTE_ARCH */
> 
> --
> 2.20.1