[PATCH] config/cn10k: align mempool elements to 128 bytes

[pbhagavatula at marvell.com]

From: Pavan Nikhilesh <pbhagavatula at marvell.com>

Mempool elements are by default aligned to CACHELINE_SIZE.
In CN10K cacheline size is 64B but the RoC requires buffers to be
aligned to 128B.
Set RTE_MEMPOOL_ALIGN to 128 to force mempool buffers to be aligned
128 bytes.

Signed-off-by: Pavan Nikhilesh <pbhagavatula at marvell.com>
---
 config/arm/meson.build | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/config/arm/meson.build b/config/arm/meson.build
index 213324d262..33afe1a9ad 100644
--- a/config/arm/meson.build
+++ b/config/arm/meson.build
@@ -276,7 +276,8 @@ soc_cn10k = {
     'implementer' : '0x41',
     'flags': [
         ['RTE_MAX_LCORE', 24],
-        ['RTE_MAX_NUMA_NODES', 1]
+        ['RTE_MAX_NUMA_NODES', 1],
+        ['RTE_MEMPOOL_ALIGN', 128]
     ],
     'part_number': '0xd49',
     'extra_march_features': ['crypto'],
-- 
2.17.1