[dpdk-dev] [PATCH v6 2/2] bus/pci: support MMIO in PCI ioport accessors
ferruh.yigit at intel.com
Tue Feb 9 15:51:01 CET 2021
On 1/29/2021 3:18 AM, 谢华伟(此时此刻） wrote:
> From: "huawei.xhw" <huawei.xhw at alibaba-inc.com>
> With IO BAR, we get PIO(programmed IO) address.
> With MMIO BAR, we get mapped virtual address.
> We distinguish PIO(Programmed IO) and MMIO(memory mapped IO) by their address like how kernel does.
> ioread/write8/16/32 is provided to access PIO/MMIO.
> By the way, for virtio on arch other than x86, BAR flag indicates PIO but is mapped.
> Signed-off-by: huawei xie <huawei.xhw at alibaba-inc.com>
> Reviewed-by: Maxime Coquelin <maxime.coquelin at redhat.com>
> +static inline void iowrite8(uint8_t val, void *addr)
> + (uint64_t)(uintptr_t)addr >= PIO_MAX ?
> + *(volatile uint8_t *)addr = val :
> + outb(val, (unsigned long)addr);
Is the 'outb_p' to 'outb' conversion intentional? And if so why?
Same of the all 'outb_p', 'outw_p', 'outl_p'.
> size = 1;
> -#if defined(RTE_ARCH_X86)
> - outb_p(*s, reg);
> - *(volatile uint8_t *)reg = *s;
> + iowrite8(*s, (void *)reg);
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