> -----Original Message-----
> From: Mahipal Challa <mchalla at marvell.com>
> Sent: Monday, February 28, 2022 9:11 AM
> To: dev at dpdk.org
> Cc: Jerin Jacob Kollanukkaran <jerinj at marvell.com>; Narayana Prasad Raju
> Athreya <pathreya at marvell.com>
> Subject: [EXT] [dpdk-dev] [PATCH v1 1/1] compress/octeontx: add octeontx2
> SoC family support
>
> External Email
>
> ----------------------------------------------------------------------
> The octeontx2 9xxx SoC family support is added.
>
> Signed-off-by: Mahipal Challa <mchalla at marvell.com>
> ---
> drivers/compress/octeontx/include/zip_regs.h | 12 ++++++++++++
> drivers/compress/octeontx/otx_zip.c | 6 +++++-
> drivers/compress/octeontx/otx_zip.h | 1 +
> drivers/compress/octeontx/otx_zip_pmd.c | 6 ++++++
> 4 files changed, 24 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/compress/octeontx/include/zip_regs.h
> b/drivers/compress/octeontx/include/zip_regs.h
> index 94a48cde66..a7fcccc055 100644
> --- a/drivers/compress/octeontx/include/zip_regs.h
> +++ b/drivers/compress/octeontx/include/zip_regs.h
> @@ -63,6 +63,18 @@ typedef union {
> uint64_t reserved_49_63 : 15;
> #endif /* Word 0 - End */
> } s;
> +
> + struct zip_vqx_sbuf_addr_s9x {
> +#if defined(__BIG_ENDIAN_BITFIELD) /* Word 0 - Big Endian */
> + uint64_t reserved_53_63 : 11;
> + uint64_t ptr : 46;
> + uint64_t off : 7;
> +#else /* Word 0 - Little Endian */
> + uint64_t off : 7;
> + uint64_t ptr : 46;
> + uint64_t reserved_53_63 : 11;
> +#endif /* Word 0 - End */
> + } s9x;
> } zip_vqx_sbuf_addr_t;
>
> /**
> diff --git a/drivers/compress/octeontx/otx_zip.c
> b/drivers/compress/octeontx/otx_zip.c
> index a9046ff351..11471dcbb4 100644
> --- a/drivers/compress/octeontx/otx_zip.c
> +++ b/drivers/compress/octeontx/otx_zip.c
> @@ -58,7 +58,11 @@ zipvf_q_init(struct zipvf_qp *qp)
> cmdq->iova = iova;
>
> que_sbuf_addr.u = 0ull;
> - que_sbuf_addr.s.ptr = (cmdq->iova >> 7);
> + if (vf->pdev->id.device_id == PCI_DEVICE_ID_OCTEONTX2_ZIPVF)
> + que_sbuf_addr.s9x.ptr = (cmdq->iova >> 7);
> + else
> + que_sbuf_addr.s.ptr = (cmdq->iova >> 7);
> +
> zip_reg_write64(vf->vbar0, ZIP_VQ_SBUF_ADDR, que_sbuf_addr.u);
>
> zip_q_enable(qp);
> diff --git a/drivers/compress/octeontx/otx_zip.h
> b/drivers/compress/octeontx/otx_zip.h
> index 118a95d738..46c80c8dc2 100644
> --- a/drivers/compress/octeontx/otx_zip.h
> +++ b/drivers/compress/octeontx/otx_zip.h
> @@ -30,6 +30,7 @@ extern int octtx_zip_logtype_driver;
> #define PCI_VENDOR_ID_CAVIUM 0x177D
> /**< PCI device id of ZIP VF */
> #define PCI_DEVICE_ID_OCTEONTX_ZIPVF 0xA037
> +#define PCI_DEVICE_ID_OCTEONTX2_ZIPVF 0xA083
>
> /* maximum number of zip vf devices */
> #define ZIP_MAX_VFS 8
> diff --git a/drivers/compress/octeontx/otx_zip_pmd.c
> b/drivers/compress/octeontx/otx_zip_pmd.c
> index f9b8f7a1ec..dff188e223 100644
> --- a/drivers/compress/octeontx/otx_zip_pmd.c
> +++ b/drivers/compress/octeontx/otx_zip_pmd.c
> @@ -85,7 +85,9 @@ zip_process_op(struct rte_comp_op *op,
> op->status = RTE_COMP_OP_STATUS_ERROR;
> }
>
> +#ifdef ZIP_DBG
> ZIP_PMD_INFO("written %d\n", zresult->s.totalbyteswritten);
> +#endif
>
> /* Update op stats */
> switch (op->status) {
> @@ -630,6 +632,10 @@ static struct rte_pci_id pci_id_octtx_zipvf_table[] = {
> RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM,
> PCI_DEVICE_ID_OCTEONTX_ZIPVF),
> },
> + {
> + RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM,
> + PCI_DEVICE_ID_OCTEONTX2_ZIPVF),
> + },
> {
> .device_id = 0
> },
> --
> 2.25.1
Acked-by: Ashish Gupta <ashishg at marvell.com>