[PATCH 1/8] common/cnxk: fix shift offset for tl3 length disable

[Jerin Jacob]

On Thu, Dec 9, 2021 at 2:43 PM Nithin Dabilpuram
<ndabilpuram at marvell.com> wrote:
>
> Fix shift offset for length disable flag in NIXX_AF_TL3X_SHAPE
> register to be 24 instead of zero similar to other level SHAPE
> registers. Also mask unused bits in adjust value.
>
> Fixes: 0885429c3028 ("common/cnxk: add NIX TM hierarchy enable/disable")
>
> Signed-off-by: Nithin Dabilpuram <ndabilpuram at marvell.com>
> Signed-off-by: Satha Rao <skoteshwar at marvell.com>


1) FIxed following warning
Is it candidate for Cc: stable at dpdk.org backport?
        common/cnxk: fix shift offset for tl3 length disable

2) Change tl3 to TL3.

Applied to dpdk-next-net-mrvl/for-next-net. Thanks


> ---
>  drivers/common/cnxk/roc_nix_tm_utils.c | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/common/cnxk/roc_nix_tm_utils.c b/drivers/common/cnxk/roc_nix_tm_utils.c
> index 543adf9..9e80c2a 100644
> --- a/drivers/common/cnxk/roc_nix_tm_utils.c
> +++ b/drivers/common/cnxk/roc_nix_tm_utils.c
> @@ -642,6 +642,7 @@ nix_tm_shaper_reg_prep(struct nix_tm_node *node,
>         else if (profile)
>                 adjust = profile->pkt_len_adj;
>
> +       adjust &= 0x1FF;
>         plt_tm_dbg("Shaper config node %s(%u) lvl %u id %u, "
>                    "pir %" PRIu64 "(%" PRIu64 "B),"
>                    " cir %" PRIu64 "(%" PRIu64 "B)"
> @@ -708,7 +709,7 @@ nix_tm_shaper_reg_prep(struct nix_tm_node *node,
>                 /* Configure RED algo */
>                 reg[k] = NIX_AF_TL3X_SHAPE(schq);
>                 regval[k] = (adjust | (uint64_t)node->red_algo << 9 |
> -                            (uint64_t)node->pkt_mode);
> +                            (uint64_t)node->pkt_mode << 24);
>                 k++;
>
>                 break;
> --
> 2.8.4
>