[dpdk-dev] [PATCH v2 1/4] drivers: add support for switch header type pre L2

[Jerin Jacob]

On Mon, Jan 3, 2022 at 11:49 AM <psatheesh at marvell.com> wrote:
>
> From: Kiran Kumar K <kirankumark at marvell.com>
>
> Adding changes to configure switch header type pre L2 for cnxk.
> Along with switch header type user needs to provide the
> offset with in the custom header that holds the size of the
> custom header and mask for the size with in the size offset.

1) with in -> within
2) Describe what is pre L2 in the commit message.
3) Change the subject to net/cnxk: support  pre L2 switch header type
Also remove "add" in other patches in the series.

4) Please rebase to fix the following

[for-next-net]dell[dpdk-next-net-mrvl] $ git pw series apply 21048
Failed to apply patch:
Applying: drivers: add support for switch header type pre L2
Applying: common/cnxk: support custom pre L2 header parsing as raw
Applying: common/cnxk: support matching VLAN existence in RTE Flow
error: sha1 information is lacking or useless
(drivers/common/cnxk/roc_npc_priv.h).
error: could not build fake ancestor
hint: Use 'git am --show-current-patch=diff' to see the failed patch
Patch failed at 0003 common/cnxk: support matching VLAN existence in RTE Flow
When you have resolved this problem, run "git am --continue".
If you prefer to skip this patch, run "git am --skip" instead.
To restore the original branch and stop patching, run "git am --abort".

>
> Signed-off-by: Kiran Kumar K <kirankumark at marvell.com>
> Reviewed-by: Satheesh Paul <psatheesh at marvell.com>
> ---
> v2:
> * Fixed checkpatch errors in commit messages
>
>  doc/guides/nics/cnxk.rst               | 25 +++++++++++++++-
>  drivers/common/cnxk/hw/npc.h           | 11 ++++---
>  drivers/common/cnxk/roc_mbox.h         |  1 +
>  drivers/common/cnxk/roc_nix.h          |  5 +++-
>  drivers/common/cnxk/roc_nix_ops.c      | 12 +++++++-
>  drivers/common/cnxk/roc_npc.h          |  8 +++++
>  drivers/net/cnxk/cnxk_ethdev.c         |  7 +++--
>  drivers/net/cnxk/cnxk_ethdev_devargs.c | 41 ++++++++++++++++++++++++++
>  8 files changed, 99 insertions(+), 11 deletions(-)
>
> diff --git a/doc/guides/nics/cnxk.rst b/doc/guides/nics/cnxk.rst
> index 2927c6cb7e..7c82cb55e1 100644
> --- a/doc/guides/nics/cnxk.rst
> +++ b/doc/guides/nics/cnxk.rst
> @@ -167,7 +167,30 @@ Runtime Config Options
>
>     With the above configuration, higig2 will be enabled on that port and the
>     traffic on this port should be higig2 traffic only. Supported switch header
> -   types are "chlen24b", "chlen90b", "dsa", "exdsa", "higig2" and "vlan_exdsa".
> +   types are "chlen24b", "chlen90b", "dsa", "exdsa", "higig2", "vlan_exdsa" and "pre_l2".
> +
> +- ``Flow pre l2 info`` (default ``0x0/0x0/0x0``)
> +
> +   In case of custom pre l2 headers, an offset, mask with in the offset and shift direction

Please explain a bit on what is pre l2 header.

> +   has to be provided within the custom header that holds the size of the custom header.
> +   This is valid only with switch header pre l2. Maximum supported offset range is 0 to 255

pre l2 -> ``pre_l2``

> +   and mask range is 1 to 255 and shift direction, 0: left shift, 1: right shift.
> +   Info format will be "offset/mask/shift direction". All parameters has to be in hexadecimal
> +   format and mask should be contiguous. Info can be configured using
> +   ``flow_pre_l2_info`` ``devargs`` parameter.
> +
> +   For example::
> +
> +      -a 0002:02:00.0,switch_header="pre_l2",flow_pre_l2_info=0x2/0x7e/0x1
> +
> +   With the above configuration, custom pre l2 header will be enabled on that port and size
> +   of the header is placed at byte offset 0x2 in the packet with mask 0x7e and right shift will
> +   be used to get the size. i.e size will be (pkt[0x2] & 0x7e) >> shift count.
> +   Shift count will be calculated based on mask and shift direction. For example if mask is 0x7c

For example -> For example,

> +   and shift direction is 1, i.e right shift, then the shift count will be 2 i.e absolute
> +   position of the right most set bit. If the mask is 0x7c and shift direction is 0, i.e left
> +   shift, then the shift count will be 1, i.e 8-n, where n is the absolute position of
> +   left most set bit.
>
>  - ``RSS tag as XOR`` (default ``0``)