[PATCH v3 01/28] common/cnxk: add multi channel support for SDP send queues

[Nithin Dabilpuram]

From: Subrahmanyam Nilla <snilla at marvell.com>

Currently only base channel number is configured as default
channel for all the SDP send queues. Due to this, packets
sent on different SQ's are landing on the same output queue
on the host. Channel number in the send queue should be
configured according to the number of queues assigned to the
SDP PF or VF device.

Signed-off-by: Subrahmanyam Nilla <snilla at marvell.com>
---
v3:
- Addressed comments from Jerin
- Removed patch 26/28 and 27/28 due to functional issues
- Added two more fixes.
v2:
- Fixed compilation issue with some compilers in patch 24/24
- Added few more fixes net/cnxk and related code in common/cnxk

 drivers/common/cnxk/roc_nix_queue.c | 7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/drivers/common/cnxk/roc_nix_queue.c b/drivers/common/cnxk/roc_nix_queue.c
index 07dab4b..76c049c 100644
--- a/drivers/common/cnxk/roc_nix_queue.c
+++ b/drivers/common/cnxk/roc_nix_queue.c
@@ -706,6 +706,7 @@ static int
 sq_cn9k_init(struct nix *nix, struct roc_nix_sq *sq, uint32_t rr_quantum,
 	     uint16_t smq)
 {
+	struct roc_nix *roc_nix = nix_priv_to_roc_nix(nix);
 	struct mbox *mbox = (&nix->dev)->mbox;
 	struct nix_aq_enq_req *aq;
 
@@ -721,7 +722,11 @@ sq_cn9k_init(struct nix *nix, struct roc_nix_sq *sq, uint32_t rr_quantum,
 	aq->sq.max_sqe_size = sq->max_sqe_sz;
 	aq->sq.smq = smq;
 	aq->sq.smq_rr_quantum = rr_quantum;
-	aq->sq.default_chan = nix->tx_chan_base;
+	if (roc_nix_is_sdp(roc_nix))
+		aq->sq.default_chan =
+			nix->tx_chan_base + (sq->qid % nix->tx_chan_cnt);
+	else
+		aq->sq.default_chan = nix->tx_chan_base;
 	aq->sq.sqe_stype = NIX_STYPE_STF;
 	aq->sq.ena = 1;
 	aq->sq.sso_ena = !!sq->sso_ena;
-- 
2.8.4