[PATCH v4 0/8] Introduce support for RISC-V architecture
Stanislaw Kardach
kda at semihalf.com
Tue May 31 16:12:59 CEST 2022
This patchset adds support for building and running DPDK on 64bit RISC-V
architecture. The initial support targets rv64gc (rv64imafdc) ISA and
was tested on SiFive Unmatched development board with the Freedom U740
SoC running Linux (freedom-u-sdk based kernel).
I have tested this codebase using DPDK unit and perf tests as well as
test-pmd, l2fwd and l3fwd examples.
The NIC attached to the DUT was Intel X520-DA2 which uses ixgbe PMD.
On the UIO side, since U740 does not have an IOMMU, I've used igb_uio,
uio_pci_generic and vfio-pci noiommu drivers.
Functional verification done using meson tests. fast-tests suite passing with
the default config.
PMD verification done using a Intel x520-DA2 NIC (ixgbe) and the test-pmd
application. Packet transfer checked using all UIO drivers available for
non-IOMMU platforms: uio_pci_generic, vfio-pci noiommu and igb_uio.
The i40e PMD driver is disabled on RISC-V as the rv64gc ISA has no vector
operations.
RISCV support is currently limited to Linux as the time measurement frequency
discovery is tied to reading a device-tree node via procfs.
Clang compilation currently not supported due to issues with missing relocation
relaxation.
Commit 1 introduces EAL and build system support for RISC-V architecture
as well as documentation updates.
Commits 2-5 add missing defines and stubs to enable RISC-V operation in
non-EAL parts.
Commit 6 adds RISC-V specific cpuflags test.
Commits 7-8 add RISC-V build testing to test-meson-builds.sh and github CI.
I appreciate Your comments and feedback.
Best Regards,
Stanislaw Kardach
v4:
- Update RISC-V cross-compilation docs to remove vendor-specific instructions
and better match the Ubuntu environment.
- Remove optional "fence" removal in the CYCLE and TIME counter reads as
those are irrelevant compared to the cost of a firmware call that allowed
such removal. The per-platform build-configuration is left in meson files
for setting '-mtune' and reference for future platforms.
- Update cross-files to specify PKG_CONFIG_LIBDIR instead of relying on the
riscv64-linux-gnu-pkg-config wrapper which was removed from Ubuntu anyway.
Also use sys_root properly instead of using c_args directly.
- Note: rte_rdtsc handling is left as it was in v3: TIME counter default,
CYCLE via compile-time option. This is mostly due to CYCLE being core-local
with values differing among cores which causes timer_autotest to run overly
long if it so happens that CYCLE on core 0 is ahead of other cores' CYCLEs.
This makes TIME counter more stable for general usage. Since CYCLE read in
userspace can be disabled by the kernel-mode (it isn't currently), the
compile-time approach is taken, same as with Aarch64.
- Added details on --no-huge tests failing in the known_issues.rst.
- Additional notes on tests:
- link_bonding_mode4_autotest succeeds and then dpdk-test fails with
segmentation fault randomly when run directly (via DPDK_TEST env
variable) with MALLOC_PERTURB_. This was not noticed in any other test
suggesting that there is a race condition somewhere in the link_bonding
PMD that leads to use-after-free (since MALLOC_PERTURB_ causes free() to
re-initialize freed memory to a given value).
- ipsec_perf_autotest currently does not check whether there is any crypto
device available (as ipsec_autotest does) and therefore fails.
v3:
- Limit test-meson-builds.sh testing to a generic rv64gc configuration.
Previous version was missing this change by mistake.
v2:
- Separate bug-fixes into separate series.
- Prevent RV64_CSRR leak to API users.
- Limit test-meson-builds.sh testing to a generic rv64gc configuration.
- Clean-up release notes and fix style issues.
[1] http://lists.infradead.org/pipermail/opensbi/2021-June/001219.html
Michal Mazurek (2):
eal: add initial support for RISC-V architecture
test/cpuflags: add test for RISC-V cpu flag
Stanislaw Kardach (6):
net/ixgbe: enable vector stubs for RISC-V
net/memif: set memfd syscall ID on RISC-V
net/tap: set BPF syscall ID for RISC-V
examples/l3fwd: enable RISC-V operation
devtools: add RISC-V to test-meson-builds.sh
ci: add RISCV64 cross compilation job
.ci/linux-build.sh | 4 +
.github/workflows/build.yml | 11 +-
MAINTAINERS | 6 +
app/test/test_cpuflags.c | 81 +++++++++++
app/test/test_xmmt_ops.h | 16 +++
config/meson.build | 2 +
config/riscv/meson.build | 131 ++++++++++++++++++
config/riscv/riscv64_linux_gcc | 17 +++
config/riscv/riscv64_sifive_u740_linux_gcc | 20 +++
devtools/test-meson-builds.sh | 4 +
doc/guides/contributing/design.rst | 2 +-
.../linux_gsg/cross_build_dpdk_for_riscv.rst | 115 +++++++++++++++
doc/guides/linux_gsg/index.rst | 1 +
doc/guides/nics/features.rst | 5 +
doc/guides/nics/features/default.ini | 1 +
doc/guides/nics/features/ixgbe.ini | 1 +
doc/guides/rel_notes/release_22_07.rst | 8 ++
drivers/net/i40e/meson.build | 6 +
drivers/net/ixgbe/ixgbe_rxtx.c | 4 +-
drivers/net/memif/rte_eth_memif.h | 2 +
drivers/net/tap/tap_bpf.h | 2 +
examples/l3fwd/l3fwd_em.c | 8 ++
examples/l3fwd/l3fwd_fib.c | 2 +
lib/eal/riscv/include/meson.build | 23 +++
lib/eal/riscv/include/rte_atomic.h | 52 +++++++
lib/eal/riscv/include/rte_byteorder.h | 44 ++++++
lib/eal/riscv/include/rte_cpuflags.h | 55 ++++++++
lib/eal/riscv/include/rte_cycles.h | 101 ++++++++++++++
lib/eal/riscv/include/rte_io.h | 21 +++
lib/eal/riscv/include/rte_mcslock.h | 18 +++
lib/eal/riscv/include/rte_memcpy.h | 63 +++++++++
lib/eal/riscv/include/rte_pause.h | 31 +++++
lib/eal/riscv/include/rte_pflock.h | 17 +++
lib/eal/riscv/include/rte_power_intrinsics.h | 22 +++
lib/eal/riscv/include/rte_prefetch.h | 50 +++++++
lib/eal/riscv/include/rte_rwlock.h | 44 ++++++
lib/eal/riscv/include/rte_spinlock.h | 67 +++++++++
lib/eal/riscv/include/rte_ticketlock.h | 21 +++
lib/eal/riscv/include/rte_vect.h | 55 ++++++++
lib/eal/riscv/meson.build | 11 ++
lib/eal/riscv/rte_cpuflags.c | 122 ++++++++++++++++
lib/eal/riscv/rte_cycles.c | 77 ++++++++++
lib/eal/riscv/rte_hypervisor.c | 13 ++
lib/eal/riscv/rte_power_intrinsics.c | 56 ++++++++
meson.build | 2 +
45 files changed, 1410 insertions(+), 4 deletions(-)
create mode 100644 config/riscv/meson.build
create mode 100644 config/riscv/riscv64_linux_gcc
create mode 100644 config/riscv/riscv64_sifive_u740_linux_gcc
create mode 100644 doc/guides/linux_gsg/cross_build_dpdk_for_riscv.rst
create mode 100644 lib/eal/riscv/include/meson.build
create mode 100644 lib/eal/riscv/include/rte_atomic.h
create mode 100644 lib/eal/riscv/include/rte_byteorder.h
create mode 100644 lib/eal/riscv/include/rte_cpuflags.h
create mode 100644 lib/eal/riscv/include/rte_cycles.h
create mode 100644 lib/eal/riscv/include/rte_io.h
create mode 100644 lib/eal/riscv/include/rte_mcslock.h
create mode 100644 lib/eal/riscv/include/rte_memcpy.h
create mode 100644 lib/eal/riscv/include/rte_pause.h
create mode 100644 lib/eal/riscv/include/rte_pflock.h
create mode 100644 lib/eal/riscv/include/rte_power_intrinsics.h
create mode 100644 lib/eal/riscv/include/rte_prefetch.h
create mode 100644 lib/eal/riscv/include/rte_rwlock.h
create mode 100644 lib/eal/riscv/include/rte_spinlock.h
create mode 100644 lib/eal/riscv/include/rte_ticketlock.h
create mode 100644 lib/eal/riscv/include/rte_vect.h
create mode 100644 lib/eal/riscv/meson.build
create mode 100644 lib/eal/riscv/rte_cpuflags.c
create mode 100644 lib/eal/riscv/rte_cycles.c
create mode 100644 lib/eal/riscv/rte_hypervisor.c
create mode 100644 lib/eal/riscv/rte_power_intrinsics.c
--
2.30.2
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