[PATCH 4/7] net/mlx5: allow hairpin Tx queue in RTE memory

[Slava Ovsiienko]

> -----Original Message-----
> From: Dariusz Sosnowski <dsosnowski at nvidia.com>
> Sent: Monday, September 19, 2022 19:37
> To: Matan Azrad <matan at nvidia.com>; Slava Ovsiienko <viacheslavo at nvidia.com>
> Cc: dev at dpdk.org
> Subject: [PATCH 4/7] net/mlx5: allow hairpin Tx queue in RTE memory
> 
> This patch adds a capability to place hairpin Tx queue in host memory
> managed by DPDK. This capability is equivalent to storing hairpin SQ's WQ
> buffer in host memory.
> 
> Hairpin Tx queue creation is extended with allocating a memory buffer of
> proper size (calculated from required number of packets and WQE BB size
> advertised in HCA capabilities).
> 
> force_memory flag of hairpin queue configuration is also supported.
> If it is set and:
> 
> - allocation of memory buffer fails,
> - or hairpin SQ creation fails,
> 
> then device start will fail. If it is unset, PMD will fallback to creating
> the hairpin SQ with WQ buffer located in unlocked device memory.
> 
> Signed-off-by: Dariusz Sosnowski <dsosnowski at nvidia.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo at nvidia.com>