[PATCH 2/4] common/qat: update common driver to support GEN5
Nishikant Nayak
nishikanta.nayak at intel.com
Wed Dec 20 14:26:14 CET 2023
Adding GEN5 specific macros which is required for updating
the support for GEN5 features.
Also this patch adds other macros which is being used by GEN5
Specific APIs.
Signed-off-by: Nishikant Nayak <nishikanta.nayak at intel.com>
---
drivers/common/qat/meson.build | 2 +
.../qat/qat_adf/adf_transport_access_macros.h | 1 +
drivers/common/qat/qat_adf/icp_qat_fw.h | 27 ++++++++++
drivers/common/qat/qat_adf/icp_qat_fw_la.h | 51 +++++++++++++++++++
drivers/common/qat/qat_common.h | 1 +
drivers/common/qat/qat_device.c | 9 ++++
6 files changed, 91 insertions(+)
diff --git a/drivers/common/qat/meson.build b/drivers/common/qat/meson.build
index 5c36fbb270..35389e5aba 100644
--- a/drivers/common/qat/meson.build
+++ b/drivers/common/qat/meson.build
@@ -82,6 +82,7 @@ sources += files(
'dev/qat_dev_gen2.c',
'dev/qat_dev_gen3.c',
'dev/qat_dev_gen4.c',
+ 'dev/qat_dev_gen5.c',
)
includes += include_directories(
'qat_adf',
@@ -108,6 +109,7 @@ if qat_crypto
'dev/qat_crypto_pmd_gen2.c',
'dev/qat_crypto_pmd_gen3.c',
'dev/qat_crypto_pmd_gen4.c',
+ 'dev/qat_crypto_pmd_gen5.c',
]
sources += files(join_paths(qat_crypto_relpath, f))
endforeach
diff --git a/drivers/common/qat/qat_adf/adf_transport_access_macros.h b/drivers/common/qat/qat_adf/adf_transport_access_macros.h
index 12a7258c60..19bd812419 100644
--- a/drivers/common/qat/qat_adf/adf_transport_access_macros.h
+++ b/drivers/common/qat/qat_adf/adf_transport_access_macros.h
@@ -47,6 +47,7 @@
#define ADF_RING_SIZE_512 0x03
#define ADF_RING_SIZE_4K 0x06
#define ADF_RING_SIZE_16K 0x08
+#define ADF_RING_SIZE_64K 0x0A
#define ADF_RING_SIZE_4M 0x10
#define ADF_MIN_RING_SIZE ADF_RING_SIZE_128
#define ADF_MAX_RING_SIZE ADF_RING_SIZE_4M
diff --git a/drivers/common/qat/qat_adf/icp_qat_fw.h b/drivers/common/qat/qat_adf/icp_qat_fw.h
index 3aa17ae041..b06b7ec989 100644
--- a/drivers/common/qat/qat_adf/icp_qat_fw.h
+++ b/drivers/common/qat/qat_adf/icp_qat_fw.h
@@ -123,6 +123,11 @@ struct icp_qat_fw_comn_resp {
#define ICP_QAT_FW_COMN_NULL_VERSION_FLAG_BITPOS 0
#define ICP_QAT_FW_COMN_NULL_VERSION_FLAG_MASK 0x1
+/* GEN5 specific Common Header fields */
+#define ICP_QAT_FW_COMN_DESC_LAYOUT_BITPOS 5
+#define ICP_QAT_FW_COMN_DESC_LAYOUT_MASK 0x3
+#define ICP_QAT_FW_COMN_GEN5_DESC_LAYOUT 3
+
#define ICP_QAT_FW_COMN_OV_SRV_TYPE_GET(icp_qat_fw_comn_req_hdr_t) \
icp_qat_fw_comn_req_hdr_t.service_type
@@ -168,6 +173,12 @@ struct icp_qat_fw_comn_resp {
(((valid) & ICP_QAT_FW_COMN_VALID_FLAG_MASK) << \
ICP_QAT_FW_COMN_VALID_FLAG_BITPOS)
+#define ICP_QAT_FW_COMN_HDR_FLAGS_BUILD_GEN5(valid, desc_layout) \
+ ((((valid) & ICP_QAT_FW_COMN_VALID_FLAG_MASK) << \
+ ICP_QAT_FW_COMN_VALID_FLAG_BITPOS) | \
+ (((desc_layout) & ICP_QAT_FW_COMN_DESC_LAYOUT_MASK) << \
+ ICP_QAT_FW_COMN_DESC_LAYOUT_BITPOS))
+
#define QAT_COMN_PTR_TYPE_BITPOS 0
#define QAT_COMN_PTR_TYPE_MASK 0x1
#define QAT_COMN_CD_FLD_TYPE_BITPOS 1
@@ -180,10 +191,20 @@ struct icp_qat_fw_comn_resp {
#define QAT_COMN_EXT_FLAGS_MASK 0x1
#define QAT_COMN_EXT_FLAGS_USED 0x1
+/* GEN5 specific Common Request Flags fields */
+#define QAT_COMN_KEYBUF_USAGE_BITPOS 1
+#define QAT_COMN_KEYBUF_USAGE_MASK 0x1
+#define QAT_COMN_KEY_BUFFER_USED 1
+
#define ICP_QAT_FW_COMN_FLAGS_BUILD(cdt, ptr) \
((((cdt) & QAT_COMN_CD_FLD_TYPE_MASK) << QAT_COMN_CD_FLD_TYPE_BITPOS) \
| (((ptr) & QAT_COMN_PTR_TYPE_MASK) << QAT_COMN_PTR_TYPE_BITPOS))
+#define ICP_QAT_FW_COMN_FLAGS_BUILD_GEN5(ptr, keybuf) \
+ ((((ptr) & QAT_COMN_PTR_TYPE_MASK) << QAT_COMN_PTR_TYPE_BITPOS) | \
+ (((keybuf) & QAT_COMN_PTR_TYPE_MASK) << \
+ QAT_COMN_KEYBUF_USAGE_BITPOS))
+
#define ICP_QAT_FW_COMN_PTR_TYPE_GET(flags) \
QAT_FIELD_GET(flags, QAT_COMN_PTR_TYPE_BITPOS, QAT_COMN_PTR_TYPE_MASK)
@@ -249,6 +270,8 @@ struct icp_qat_fw_comn_resp {
#define QAT_COMN_RESP_CMP_END_OF_LAST_BLK_MASK 0x1
#define QAT_COMN_RESP_UNSUPPORTED_REQUEST_BITPOS 2
#define QAT_COMN_RESP_UNSUPPORTED_REQUEST_MASK 0x1
+#define QAT_COMN_RESP_INVALID_PARAM_BITPOS 1
+#define QAT_COMN_RESP_INVALID_PARAM_MASK 0x1
#define QAT_COMN_RESP_XLT_WA_APPLIED_BITPOS 0
#define QAT_COMN_RESP_XLT_WA_APPLIED_MASK 0x1
@@ -280,6 +303,10 @@ struct icp_qat_fw_comn_resp {
QAT_FIELD_GET(status, QAT_COMN_RESP_UNSUPPORTED_REQUEST_BITPOS, \
QAT_COMN_RESP_UNSUPPORTED_REQUEST_MASK)
+#define ICP_QAT_FW_COMN_RESP_INVALID_PARAM_STAT_GET(status) \
+ QAT_FIELD_GET(status, QAT_COMN_RESP_INVALID_PARAM_BITPOS, \
+ QAT_COMN_RESP_INVALID_PARAM_MASK)
+
#define ICP_QAT_FW_COMN_STATUS_FLAG_OK 0
#define ICP_QAT_FW_COMN_STATUS_FLAG_ERROR 1
#define ICP_QAT_FW_COMN_STATUS_CMP_END_OF_LAST_BLK_FLAG_CLR 0
diff --git a/drivers/common/qat/qat_adf/icp_qat_fw_la.h b/drivers/common/qat/qat_adf/icp_qat_fw_la.h
index 70f0effa62..f61241d12a 100644
--- a/drivers/common/qat/qat_adf/icp_qat_fw_la.h
+++ b/drivers/common/qat/qat_adf/icp_qat_fw_la.h
@@ -22,11 +22,18 @@ enum icp_qat_fw_la_cmd_id {
ICP_QAT_FW_LA_CMD_DELIMITER = 18
};
+/* In GEN5 Command ID 4 corresponds to AEAD */
+#define ICP_QAT_FW_LA_CMD_AEAD 4
+
#define ICP_QAT_FW_LA_ICV_VER_STATUS_PASS ICP_QAT_FW_COMN_STATUS_FLAG_OK
#define ICP_QAT_FW_LA_ICV_VER_STATUS_FAIL ICP_QAT_FW_COMN_STATUS_FLAG_ERROR
#define ICP_QAT_FW_LA_TRNG_STATUS_PASS ICP_QAT_FW_COMN_STATUS_FLAG_OK
#define ICP_QAT_FW_LA_TRNG_STATUS_FAIL ICP_QAT_FW_COMN_STATUS_FLAG_ERROR
+/* GEN5 Hash, HMAC and GCM Verification Status */
+#define ICP_QAT_FW_LA_VER_STATUS_FAIL ICP_QAT_FW_COMN_STATUS_FLAG_OK
+
+
struct icp_qat_fw_la_bulk_req {
struct icp_qat_fw_comn_req_hdr comn_hdr;
struct icp_qat_fw_comn_req_hdr_cd_pars cd_pars;
@@ -81,6 +88,18 @@ struct icp_qat_fw_la_bulk_req {
#define ICP_QAT_FW_LA_PARTIAL_END 2
#define QAT_LA_PARTIAL_BITPOS 0
#define QAT_LA_PARTIAL_MASK 0x3
+
+/* GEN5 specific Crypto Flags fields */
+#define ICP_QAT_FW_SYM_AEAD_ALGO_BITPOS 6
+#define ICP_QAT_FW_SYM_AEAD_ALGO_MASK 0x3
+#define ICP_QAT_FW_SYM_IV_SIZE_BITPOS 9
+#define ICP_QAT_FW_SYM_IV_SIZE_MASK 0x3
+#define ICP_QAT_FW_SYM_IV_IN_DESC_BITPOS 11
+#define ICP_QAT_FW_SYM_IV_IN_DESC_MASK 0x1
+#define ICP_QAT_FW_SYM_IV_IN_DESC_VALID 1
+#define ICP_QAT_FW_SYM_DIRECTION_BITPOS 15
+#define ICP_QAT_FW_SYM_DIRECTION_MASK 0x1
+
#define ICP_QAT_FW_LA_FLAGS_BUILD(zuc_proto, gcm_iv_len, auth_rslt, proto, \
cmp_auth, ret_auth, update_state, \
ciph_iv, ciphcfg, partial) \
@@ -188,6 +207,23 @@ struct icp_qat_fw_la_bulk_req {
QAT_FIELD_SET(flags, val, QAT_LA_PARTIAL_BITPOS, \
QAT_LA_PARTIAL_MASK)
+/* GEN5 specific Crypto Flags operations */
+#define ICP_QAT_FW_SYM_AEAD_ALGO_SET(flags, val) \
+ QAT_FIELD_SET(flags, val, ICP_QAT_FW_SYM_AEAD_ALGO_BITPOS, \
+ ICP_QAT_FW_SYM_AEAD_ALGO_MASK)
+
+#define ICP_QAT_FW_SYM_IV_SIZE_SET(flags, val) \
+ QAT_FIELD_SET(flags, val, ICP_QAT_FW_SYM_IV_SIZE_BITPOS, \
+ ICP_QAT_FW_SYM_IV_SIZE_MASK)
+
+#define ICP_QAT_FW_SYM_IV_IN_DESC_FLAG_SET(flags, val) \
+ QAT_FIELD_SET(flags, val, ICP_QAT_FW_SYM_IV_IN_DESC_BITPOS, \
+ ICP_QAT_FW_SYM_IV_IN_DESC_MASK)
+
+#define ICP_QAT_FW_SYM_DIR_FLAG_SET(flags, val) \
+ QAT_FIELD_SET(flags, val, ICP_QAT_FW_SYM_DIRECTION_BITPOS, \
+ ICP_QAT_FW_SYM_DIRECTION_MASK)
+
#define QAT_FW_LA_MODE2 1
#define QAT_FW_LA_NO_MODE2 0
#define QAT_FW_LA_MODE2_MASK 0x1
@@ -410,4 +446,19 @@ struct icp_qat_fw_la_cipher_20_req_params {
uint8_t spc_auth_res_sz;
};
+struct icp_qat_fw_la_cipher_30_req_params {
+ uint32_t spc_aad_sz;
+ uint8_t cipher_length;
+ uint8_t reserved[2];
+ uint8_t spc_auth_res_sz;
+ union {
+ uint32_t cipher_IV_array[ICP_QAT_FW_NUM_LONGWORDS_4];
+ struct {
+ uint64_t cipher_IV_ptr;
+ uint64_t resrvd1;
+ } s;
+
+ } u;
+};
+
#endif
diff --git a/drivers/common/qat/qat_common.h b/drivers/common/qat/qat_common.h
index 9411a79301..dc48a2e1ee 100644
--- a/drivers/common/qat/qat_common.h
+++ b/drivers/common/qat/qat_common.h
@@ -21,6 +21,7 @@ enum qat_device_gen {
QAT_GEN2,
QAT_GEN3,
QAT_GEN4,
+ QAT_GEN5,
QAT_N_GENS
};
diff --git a/drivers/common/qat/qat_device.c b/drivers/common/qat/qat_device.c
index f55dc3c6f0..d4f5391d12 100644
--- a/drivers/common/qat/qat_device.c
+++ b/drivers/common/qat/qat_device.c
@@ -62,6 +62,12 @@ static const struct rte_pci_id pci_id_qat_map[] = {
{
RTE_PCI_DEVICE(0x8086, 0x4945),
},
+ {
+ RTE_PCI_DEVICE(0x8086, 0x1454), /* GEN5: AVFs */
+ },
+ {
+ RTE_PCI_DEVICE(0x8086, 0x1456), /* GEN5: CPF */
+ },
{.device_id = 0},
};
@@ -199,6 +205,9 @@ pick_gen(const struct rte_pci_device *pci_dev)
case 0x4943:
case 0x4945:
return QAT_GEN4;
+ case 0x1454: /* QAT30: AVF */
+ case 0x1456: /* QAT30: CPF-mdev */
+ return QAT_GEN5;
default:
QAT_LOG(ERR, "Invalid dev_id, can't determine generation");
return QAT_N_GENS;
--
2.25.1
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