[PATCH v2 0/9] crypto/mlx5: support AES-GCM
Suanming Mou
suanmingm at nvidia.com
Tue Jun 20 11:55:13 CEST 2023
Hi Akhil,
Maybe due to "To" is empty, it was not collected correctly to the ML. But it was in my inbox, and you were cced.
Thanks,
Suanming
> -----Original Message-----
> From: Suanming Mou <suanmingm at nvidia.com>
> Sent: Tuesday, June 20, 2023 9:23 AM
> Cc: Raslan Darawsheh <rasland at nvidia.com>; dev at dpdk.org;
> gakhil at marvell.com
> Subject: [PATCH v2 0/9] crypto/mlx5: support AES-GCM
>
> AES-GCM provides both authenticated encryption and the ability to check the
> integrity and authentication of additional authenticated data (AAD) that is sent in
> the clear.
>
> The crypto operations are performed with crypto WQE. If the input buffers(AAD,
> mbuf, digest) are not contiguous and there is no enough headroom or tailroom for
> AAD or digest, as the requirement from FW, an UMR WQE is needed to generate
> contiguous address space for crypto WQE.
> The UMR WQE and crypto WQE are handled in two different QPs.
>
> The QP for UMR operation contains two types of WQE, UMR and SEND_EN WQE.
> The WQEs are built dynamically according to the crypto operation buffer address.
> Crypto operation with non-contiguous buffers will
> have its own UMR WQE, while the operation with contiguous buffers
> doesn't need the UMR WQE. Once the all the operations WQE in the enqueue
> burst built finishes, if any UMR WQEs are built, additional SEND_EN WQE will be
> as the final WQE of the burst in the UMR QP.
> The purpose of that SEND_EN WQE is to trigger the crypto QP processing with the
> UMR ready input memory address space buffers.
>
> The QP for crypto operations contains only the crypto WQE and the QP WQEs are
> built as fixed in QP setup. The QP processing is triggered by doorbell ring or the
> SEND_EN WQE from UMR QP.
>
> v2:
> - split XTS and GCM code to different file.
> - add headroom and tailroom optimize.
>
> v3:
> - fix AES-GCM 128b key creation.
>
> Suanming Mou (9):
> common/mlx5: export memory region lookup by address
> crypto/mlx5: split AES-XTS
> crypto/mlx5: add AES-GCM query and initialization
> crypto/mlx5: add AES-GCM encryption key
> crypto/mlx5: add AES-GCM session configure
> common/mlx5: add WQE-based QP synchronous basics
> crypto/mlx5: add queue pair setup for GCM
> crypto/mlx5: add enqueue and dequeue operations
> crypto/mlx5: enable AES-GCM capability
>
> doc/guides/cryptodevs/mlx5.rst | 48 +-
> doc/guides/rel_notes/release_23_07.rst | 1 +
> drivers/common/mlx5/mlx5_common_mr.c | 2 +-
> drivers/common/mlx5/mlx5_common_mr.h | 5 +
> drivers/common/mlx5/mlx5_devx_cmds.c | 21 +
> drivers/common/mlx5/mlx5_devx_cmds.h | 16 +
> drivers/common/mlx5/mlx5_prm.h | 65 +-
> drivers/common/mlx5/version.map | 3 +
> drivers/crypto/mlx5/meson.build | 2 +
> drivers/crypto/mlx5/mlx5_crypto.c | 673 ++---------------
> drivers/crypto/mlx5/mlx5_crypto.h | 101 ++-
> drivers/crypto/mlx5/mlx5_crypto_dek.c | 102 ++-
> drivers/crypto/mlx5/mlx5_crypto_gcm.c | 997 +++++++++++++++++++++++++
> drivers/crypto/mlx5/mlx5_crypto_xts.c | 645 ++++++++++++++++
> 14 files changed, 2016 insertions(+), 665 deletions(-) create mode 100644
> drivers/crypto/mlx5/mlx5_crypto_gcm.c
> create mode 100644 drivers/crypto/mlx5/mlx5_crypto_xts.c
>
> --
> 2.25.1
More information about the dev
mailing list