[EXT] [PATCH v1] bus/pci: add function to enable/disable PASID

[Jerin Jacob Kollanukkaran]

> -----Original Message-----
> From: Abdullah Sevincer <abdullah.sevincer at intel.com>
> Sent: Friday, November 3, 2023 10:34 PM
> To: dev at dpdk.org
> Cc: Jerin Jacob Kollanukkaran <jerinj at marvell.com>;
> mike.ximing.chen at intel.com; bruce.richardson at intel.com;
> thomas at monjalon.net; Abdullah Sevincer <abdullah.sevincer at intel.com>
> Subject: [EXT] [PATCH v1] bus/pci: add function to enable/disable PASID
> 
> External Email
> 
> ----------------------------------------------------------------------
> This commit implements an internal api to enable and disable PASID for a
> device e.g. DLB Device.
> 
> For kernels when PASID enabled by default it breaks DLB functionality, hence
> disabling PASID is required for DLB to function properly.
> 
> PASID capability is not exposed to users hence offset can not be retrieved by
> rte_pci_find_ext_capability() api. Therefore, api implemented in this commit
> accepts an offset for PASID with an enable flag which is used to enable/disable
> PASID.
> 
> Signed-off-by: Abdullah Sevincer <abdullah.sevincer at intel.com>
> ---
> +/**
> + * Enable/Disable PASID.
> + *
> + * @param offset
> + *   Offset of the PASID external capability.
> + * @param enable
> + *   Flag to enable or disable PASID.
> + */
> +__rte_internal
> +int rte_pci_set_pasid(const struct rte_pci_device *dev, off_t offset,
> +bool enable);

May be rte_pci_pasid_ena_dis(const struct rte_pci_device *dev, off_t offset,
bool enable) could be better name as it NOT setting the pasid

> +#define RTE_PCI_PASID_CAP_OFFSET        0x148   /* PASID capability offset */

Is this fixed for all PCIe device? Offset will vary based on number of capabilities present in a given device, if so,
move this to event/dlb.