[PATCH v2 07/15] pci: define some command constants

[Xia, Chenbo]

> -----Original Message-----
> From: David Marchand <david.marchand at redhat.com>
> Sent: Monday, August 21, 2023 7:36 PM
> To: dev at dpdk.org
> Cc: thomas at monjalon.net; ferruh.yigit at amd.com; Xia, Chenbo
> <chenbo.xia at intel.com>; nipun.gupta at amd.com; Richardson, Bruce
> <bruce.richardson at intel.com>; Burakov, Anatoly <anatoly.burakov at intel.com>;
> McDaniel, Timothy <timothy.mcdaniel at intel.com>; Gaetan Rivet
> <grive at u256.net>
> Subject: [PATCH v2 07/15] pci: define some command constants
> 
> Define some PCI command constants and use them in existing drivers.
> 
> Signed-off-by: David Marchand <david.marchand at redhat.com>
> Acked-by: Bruce Richardson <bruce.richardson at intel.com>
> ---
>  drivers/bus/pci/linux/pci_vfio.c  | 8 ++++----
>  drivers/event/dlb2/pf/dlb2_main.c | 8 +++-----
>  lib/pci/rte_pci.h                 | 6 ++++--
>  3 files changed, 11 insertions(+), 11 deletions(-)
> 
> diff --git a/drivers/bus/pci/linux/pci_vfio.c
> b/drivers/bus/pci/linux/pci_vfio.c
> index 7881b7a946..bf91492dd9 100644
> --- a/drivers/bus/pci/linux/pci_vfio.c
> +++ b/drivers/bus/pci/linux/pci_vfio.c
> @@ -156,18 +156,18 @@ pci_vfio_enable_bus_memory(struct rte_pci_device
> *dev, int dev_fd)
>  		return -1;
>  	}
> 
> -	ret = pread64(dev_fd, &cmd, sizeof(cmd), offset + PCI_COMMAND);
> +	ret = pread64(dev_fd, &cmd, sizeof(cmd), offset + RTE_PCI_COMMAND);
> 
>  	if (ret != sizeof(cmd)) {
>  		RTE_LOG(ERR, EAL, "Cannot read command from PCI config
> space!\n");
>  		return -1;
>  	}
> 
> -	if (cmd & PCI_COMMAND_MEMORY)
> +	if (cmd & RTE_PCI_COMMAND_MEMORY)
>  		return 0;
> 
> -	cmd |= PCI_COMMAND_MEMORY;
> -	ret = pwrite64(dev_fd, &cmd, sizeof(cmd), offset + PCI_COMMAND);
> +	cmd |= RTE_PCI_COMMAND_MEMORY;
> +	ret = pwrite64(dev_fd, &cmd, sizeof(cmd), offset + RTE_PCI_COMMAND);
> 
>  	if (ret != sizeof(cmd)) {
>  		RTE_LOG(ERR, EAL, "Cannot write command to PCI config
> space!\n");
> diff --git a/drivers/event/dlb2/pf/dlb2_main.c
> b/drivers/event/dlb2/pf/dlb2_main.c
> index c6606a9bee..6dbaa2ff97 100644
> --- a/drivers/event/dlb2/pf/dlb2_main.c
> +++ b/drivers/event/dlb2/pf/dlb2_main.c
> @@ -33,7 +33,6 @@
>  #define DLB2_PCI_EXP_DEVCTL2 40
>  #define DLB2_PCI_LNKCTL2 48
>  #define DLB2_PCI_SLTCTL2 56
> -#define DLB2_PCI_CMD 4
>  #define DLB2_PCI_EXP_DEVSTA 10
>  #define DLB2_PCI_EXP_DEVSTA_TRPND 0x20
>  #define DLB2_PCI_EXP_DEVCTL_BCR_FLR 0x8000
> @@ -47,7 +46,6 @@
>  #define DLB2_PCI_ERR_ROOT_STATUS         0x30
>  #define DLB2_PCI_ERR_COR_STATUS          0x10
>  #define DLB2_PCI_ERR_UNCOR_STATUS        0x4
> -#define DLB2_PCI_COMMAND_INTX_DISABLE    0x400
>  #define DLB2_PCI_ACS_CAP                 0x4
>  #define DLB2_PCI_ACS_CTRL                0x6
>  #define DLB2_PCI_ACS_SV                  0x1
> @@ -286,7 +284,7 @@ dlb2_pf_reset(struct dlb2_dev *dlb2_dev)
> 
>  	/* clear the PCI command register before issuing the FLR */
> 
> -	off = DLB2_PCI_CMD;
> +	off = RTE_PCI_COMMAND;
>  	cmd = 0;
>  	if (rte_pci_write_config(pdev, &cmd, 2, off) != 2) {
>  		DLB2_LOG_ERR("[%s()] failed to write the pci command\n",
> @@ -468,9 +466,9 @@ dlb2_pf_reset(struct dlb2_dev *dlb2_dev)
>  		}
>  	}
> 
> -	off = DLB2_PCI_CMD;
> +	off = RTE_PCI_COMMAND;
>  	if (rte_pci_read_config(pdev, &cmd, 2, off) == 2) {
> -		cmd &= ~DLB2_PCI_COMMAND_INTX_DISABLE;
> +		cmd &= ~RTE_PCI_COMMAND_INTX_DISABLE;
>  		if (rte_pci_write_config(pdev, &cmd, 2, off) != 2) {
>  			DLB2_LOG_ERR("[%s()] failed to write the pci command\n",
>  			       __func__);
> diff --git a/lib/pci/rte_pci.h b/lib/pci/rte_pci.h
> index 41dc725cc4..9eb8f85ceb 100644
> --- a/lib/pci/rte_pci.h
> +++ b/lib/pci/rte_pci.h
> @@ -37,8 +37,10 @@ extern "C" {
>  #define RTE_PCI_STATUS		0x06	/* 16 bits */
>  #define RTE_PCI_CAPABILITY_LIST	0x34	/* 32 bits */
> 
> -/* PCI Command Register */
> -#define RTE_PCI_COMMAND_MASTER	0x4	/* Bus Master Enable */
> +/* PCI Command Register (RTE_PCI_COMMAND) */
> +#define RTE_PCI_COMMAND_MEMORY		0x2	/* Enable response in
> Memory space */
> +#define RTE_PCI_COMMAND_MASTER		0x4	/* Bus Master Enable */
> +#define RTE_PCI_COMMAND_INTX_DISABLE	0x400	/* INTx Emulation Disable
> */
> 
>  /* PCI Status Register (RTE_PCI_STATUS) */
>  #define RTE_PCI_STATUS_CAP_LIST		0x10	/* Support Capability List
> */
> --
> 2.41.0

Reviewed-by: Chenbo Xia <chenbo.xia at intel.com>