[PATCH v5 05/11] common/idpf/base: remove mailbox registers

[Simei Su]

Remove mailbox register offsets because individual drivers will define
the offsets based on how registers address the registers.

Signed-off-by: Madhu Chittim <madhu.chittim at intel.com>
Signed-off-by: Simei Su <simei.su at intel.com>
Acked-by: Beilei Xing <beilei.xing at intel.com>
---
 .mailmap                             |  1 +
 drivers/common/idpf/base/siov_regs.h | 13 ++-----------
 2 files changed, 3 insertions(+), 11 deletions(-)

diff --git a/.mailmap b/.mailmap
index 91d8cca78f..d8782cd67e 100644
--- a/.mailmap
+++ b/.mailmap
@@ -1642,3 +1642,4 @@ Zyta Szpak <zyta at marvell.com> <zr at semihalf.com> <zyta.szpak at semihalf.com>
 Jayaprakash Shanmugam <jayaprakash.shanmugam at intel.com>
 Zhenning Xiao <zhenning.xiao at intel.com>
 Josh Hay <joshua.a.hay at intel.com>
+Madhu Chittim <madhu.chittim at intel.com>
diff --git a/drivers/common/idpf/base/siov_regs.h b/drivers/common/idpf/base/siov_regs.h
index fad329601a..7e1ae2e300 100644
--- a/drivers/common/idpf/base/siov_regs.h
+++ b/drivers/common/idpf/base/siov_regs.h
@@ -4,16 +4,6 @@
 #ifndef _SIOV_REGS_H_
 #define _SIOV_REGS_H_
 #define VDEV_MBX_START			0x20000 /* Begin at 128KB */
-#define VDEV_MBX_ATQBAL			(VDEV_MBX_START + 0x0000)
-#define VDEV_MBX_ATQBAH			(VDEV_MBX_START + 0x0004)
-#define VDEV_MBX_ATQLEN			(VDEV_MBX_START + 0x0008)
-#define VDEV_MBX_ATQH			(VDEV_MBX_START + 0x000C)
-#define VDEV_MBX_ATQT			(VDEV_MBX_START + 0x0010)
-#define VDEV_MBX_ARQBAL			(VDEV_MBX_START + 0x0014)
-#define VDEV_MBX_ARQBAH			(VDEV_MBX_START + 0x0018)
-#define VDEV_MBX_ARQLEN			(VDEV_MBX_START + 0x001C)
-#define VDEV_MBX_ARQH			(VDEV_MBX_START + 0x0020)
-#define VDEV_MBX_ARQT			(VDEV_MBX_START + 0x0024)
 #define VDEV_GET_RSTAT			0x21000 /* 132KB for RSTAT */
 
 /* Begin at offset after 1MB (after 256 4k pages) */
@@ -43,5 +33,6 @@
 #define VDEV_INT_ITR_1(_i)		(VDEV_INT_DYN_START + ((_i) * 0x1000) + 0x08)
 #define VDEV_INT_ITR_2(_i)		(VDEV_INT_DYN_START + ((_i) * 0x1000) + 0x0C)
 
-/* Next offset to begin at 42MB (0x2A00000) */
+#define SIOV_REG_BAR_SIZE               0x2A00000
+/* Next offset to begin at 42MB + 4K (0x2A00000 + 0x1000) */
 #endif /* _SIOV_REGS_H_ */
-- 
2.25.1