[PATCH] common/cnxk: use atomic load acquire in batch ops
Nawal Kishor
nkishor at marvell.com
Fri Aug 23 08:51:04 CEST 2024
In roc batch alloc wait code, __ATOMIC_RELAXED is changed to
__ATOMIC_ACQUIRE in order to avoid potential out of order loads.
Signed-off-by: Nawal Kishor <nkishor at marvell.com>
---
.mailmap | 1 +
drivers/common/cnxk/roc_npa.h | 2 +-
2 files changed, 2 insertions(+), 1 deletion(-)
diff --git a/.mailmap b/.mailmap
index 4a508bafad..14226ccd2d 100644
--- a/.mailmap
+++ b/.mailmap
@@ -1046,6 +1046,7 @@ Natanael Copa <ncopa at alpinelinux.org>
Nathan Brown <nathan.brown at arm.com>
Nathan Law <nlaw at brocade.com>
Nathan Skrzypczak <nathan.skrzypczak at gmail.com>
+Nawal Kishor <nkishor at marvell.com>
Neel Patel <neel.patel at amd.com> <neel at pensando.io>
Neil Horman <nhorman at tuxdriver.com>
Nelio Laranjeiro <nelio.laranjeiro at 6wind.com>
diff --git a/drivers/common/cnxk/roc_npa.h b/drivers/common/cnxk/roc_npa.h
index 4ad5f044b5..ebc2a62536 100644
--- a/drivers/common/cnxk/roc_npa.h
+++ b/drivers/common/cnxk/roc_npa.h
@@ -247,7 +247,7 @@ roc_npa_batch_alloc_wait(uint64_t *cache_line, unsigned int wait_us)
/* Batch alloc status code is updated in bits [5:6] of the first word
* of the 128 byte cache line.
*/
- while (((__atomic_load_n(cache_line, __ATOMIC_RELAXED) >> 5) & 0x3) ==
+ while (((__atomic_load_n(cache_line, __ATOMIC_ACQUIRE) >> 5) & 0x3) ==
ALLOC_CCODE_INVAL)
if (wait_us && (plt_tsc_cycles() - start) >= ticks)
break;
--
2.34.1
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