[PATCH v1] net/mlx5/hws: match VXLAN all fields

[Rongwei Liu]

Support VxLAN all fields support.
To match GBP or GPE extension, the user needs to set
the right UDP destination port plus the desired VxLAN
flag bits.

Signed-off-by: Rongwei Liu <rongweil at nvidia.com>
Reviewed-by: Alex Vesker <valex at nvidia.com>
Acked-by: Dariusz Sosnowski <dsosnowski at nvidia.com>
---
 doc/guides/nics/mlx5.rst              | 18 +++++++-------
 drivers/net/mlx5/hws/mlx5dr_definer.c | 36 ++++++---------------------
 drivers/net/mlx5/hws/mlx5dr_definer.h |  4 +--
 3 files changed, 19 insertions(+), 39 deletions(-)

diff --git a/doc/guides/nics/mlx5.rst b/doc/guides/nics/mlx5.rst
index 9b2fe07fd3..dcc1beb812 100644
--- a/doc/guides/nics/mlx5.rst
+++ b/doc/guides/nics/mlx5.rst
@@ -302,21 +302,21 @@ Limitations
   size and ``txq_inline_min`` settings and may be from 2 (worst case forced by maximal
   inline settings) to 58.
 
-- Match on VXLAN supports the following fields only:
+- Match on VXLAN supports any bits in the tunnel header
 
-     - VNI
-     - Last reserved 8-bits
-
-  Last reserved 8-bits matching is only supported When using DV flow
-  engine (``dv_flow_en`` = 1).
-  For ConnectX-5, the UDP destination port must be the standard one (4789).
-  Group zero's behavior may differ which depends on FW.
-  Matching value equals 0 (value & mask) is not supported.
+   - Flag 8-bits and first 24-bits reserved fields matching is only supported When using DV flow
+     engine (``dv_flow_en`` = 2).
+   - For ConnectX-5, the UDP destination port must be the standard one (4789).
+   - Group zero's behavior may differ which depends on FW.
+   - Default UDP destination is 4789 if not explicitly specified.
+   - User should set different flags when matching on VXLAN-GPE/GBP: like I and GPE bits for
+     GPE and G bit for GBP.
 
 - Matching on VXLAN-GPE header fields:
 
      - ``rsvd0``/``rsvd1`` matching support depends on FW version
        when using DV flow engine (``dv_flow_en`` = 1).
+     - ``protocol`` should be explicitly specified in HWS steering (``dv_flow_en`` = 2).
 
 - L3 VXLAN and VXLAN-GPE tunnels cannot be supported together with MPLSoGRE and MPLSoUDP.
 
diff --git a/drivers/net/mlx5/hws/mlx5dr_definer.c b/drivers/net/mlx5/hws/mlx5dr_definer.c
index a0f95c6923..63381c1111 100644
--- a/drivers/net/mlx5/hws/mlx5dr_definer.c
+++ b/drivers/net/mlx5/hws/mlx5dr_definer.c
@@ -203,7 +203,8 @@ struct mlx5dr_definer_conv_data {
 	X(SET,		gtp_next_ext_hdr,	GTP_PDU_SC,		rte_flow_item_gtp_psc) \
 	X(SET,		gtp_ext_hdr_pdu,	v->hdr.type,		rte_flow_item_gtp_psc) \
 	X(SET,		gtp_ext_hdr_qfi,	v->hdr.qfi,		rte_flow_item_gtp_psc) \
-	X(SET,		vxlan_flags,		v->flags,		rte_flow_item_vxlan) \
+	X(SET_BE32,	vxlan_vx_flags,		v->hdr.vx_flags,	rte_flow_item_vxlan) \
+	X(SET_BE32,	vxlan_vx_vni,		v->hdr.vx_vni,		rte_flow_item_vxlan) \
 	X(SET,		vxlan_udp_port,		UDP_VXLAN_PORT,		rte_flow_item_vxlan) \
 	X(SET,		vxlan_gpe_udp_port,	UDP_VXLAN_GPE_PORT,	rte_flow_item_vxlan_gpe) \
 	X(SET,		vxlan_gpe_flags,	v->flags,		rte_flow_item_vxlan_gpe) \
@@ -600,16 +601,6 @@ mlx5dr_definer_gre_key_set(struct mlx5dr_definer_fc *fc,
 	DR_SET_BE32(tag, *v, fc->byte_off, fc->bit_off, fc->bit_mask);
 }
 
-static void
-mlx5dr_definer_vxlan_vni_set(struct mlx5dr_definer_fc *fc,
-			     const void *item_spec,
-			     uint8_t *tag)
-{
-	const struct rte_flow_item_vxlan *v = item_spec;
-
-	memcpy(tag + fc->byte_off, v->vni, sizeof(v->vni));
-}
-
 static void
 mlx5dr_definer_ipv6_tos_set(struct mlx5dr_definer_fc *fc,
 			    const void *item_spec,
@@ -1555,13 +1546,6 @@ mlx5dr_definer_conv_item_vxlan(struct mlx5dr_definer_conv_data *cd,
 	struct mlx5dr_definer_fc *fc;
 	bool inner = cd->tunnel;
 
-	if (m && (m->rsvd0[0] != 0 || m->rsvd0[1] != 0 || m->rsvd0[2] != 0 ||
-	    m->rsvd1 != 0)) {
-		DR_LOG(ERR, "reserved fields are not supported");
-		rte_errno = ENOTSUP;
-		return rte_errno;
-	}
-
 	if (inner) {
 		DR_LOG(ERR, "Inner VXLAN item not supported");
 		rte_errno = ENOTSUP;
@@ -1590,22 +1574,18 @@ mlx5dr_definer_conv_item_vxlan(struct mlx5dr_definer_conv_data *cd,
 	if (!m)
 		return 0;
 
-	if (m->flags) {
-		fc = &cd->fc[MLX5DR_DEFINER_FNAME_VXLAN_FLAGS];
+	if (m->hdr.vx_flags) {
+		fc = &cd->fc[MLX5DR_DEFINER_FNAME_VXLAN_DW0];
 		fc->item_idx = item_idx;
-		fc->tag_set = &mlx5dr_definer_vxlan_flags_set;
+		fc->tag_set = &mlx5dr_definer_vxlan_vx_flags_set;
 		DR_CALC_SET_HDR(fc, tunnel_header, tunnel_header_0);
-		fc->bit_mask = __mlx5_mask(header_vxlan, flags);
-		fc->bit_off = __mlx5_dw_bit_off(header_vxlan, flags);
 	}
 
-	if (!is_mem_zero(m->vni, 3)) {
-		fc = &cd->fc[MLX5DR_DEFINER_FNAME_VXLAN_VNI];
+	if (m->hdr.vx_vni) {
+		fc = &cd->fc[MLX5DR_DEFINER_FNAME_VXLAN_DW1];
 		fc->item_idx = item_idx;
-		fc->tag_set = &mlx5dr_definer_vxlan_vni_set;
+		fc->tag_set = &mlx5dr_definer_vxlan_vx_vni_set;
 		DR_CALC_SET_HDR(fc, tunnel_header, tunnel_header_1);
-		fc->bit_mask = __mlx5_mask(header_vxlan, vni);
-		fc->bit_off = __mlx5_dw_bit_off(header_vxlan, vni);
 	}
 
 	return 0;
diff --git a/drivers/net/mlx5/hws/mlx5dr_definer.h b/drivers/net/mlx5/hws/mlx5dr_definer.h
index a42ba9b81a..8f34ea64c8 100644
--- a/drivers/net/mlx5/hws/mlx5dr_definer.h
+++ b/drivers/net/mlx5/hws/mlx5dr_definer.h
@@ -122,8 +122,8 @@ enum mlx5dr_definer_fname {
 	MLX5DR_DEFINER_FNAME_FLEX_PARSER_6,
 	MLX5DR_DEFINER_FNAME_FLEX_PARSER_7,
 	MLX5DR_DEFINER_FNAME_VPORT_REG_C_0,
-	MLX5DR_DEFINER_FNAME_VXLAN_FLAGS,
-	MLX5DR_DEFINER_FNAME_VXLAN_VNI,
+	MLX5DR_DEFINER_FNAME_VXLAN_DW0,
+	MLX5DR_DEFINER_FNAME_VXLAN_DW1,
 	MLX5DR_DEFINER_FNAME_VXLAN_GPE_FLAGS,
 	MLX5DR_DEFINER_FNAME_VXLAN_GPE_RSVD0,
 	MLX5DR_DEFINER_FNAME_VXLAN_GPE_PROTO,
-- 
2.27.0