[PATCH v2 04/25] net/axgbe: update DMA coherency values

[Sebastian, Selwin]

[AMD Official Use Only - AMD Internal Distribution Only]

Acked-by: Selwin Sebastian<selwin.sebastian at amd.com>

-----Original Message-----
From: Ande, Venkat Kumar <VenkatKumar.Ande at amd.com>
Sent: Tuesday, May 7, 2024 6:13 PM
To: dev at dpdk.org
Cc: Sebastian, Selwin <Selwin.Sebastian at amd.com>; Ande, Venkat Kumar <VenkatKumar.Ande at amd.com>; stable at dpdk.org
Subject: [PATCH v2 04/25] net/axgbe: update DMA coherency values

Based on the IOMMU configuration, the current cache control settings can result in possible coherency issues. The hardware team has recommended new settings for the PCI device path to eliminate the issue.

Without the fix the user will get incorrect data in TSO functionality

Fixes: 7c4158a5b592 ("net/axgbe: add DMA programming and start/stop")
Cc: stable at dpdk.org

Signed-off-by: Venkat Kumar Ande <venkatkumar.ande at amd.com>
---
 drivers/net/axgbe/axgbe_dev.c | 20 +++++++++-----------
 1 file changed, 9 insertions(+), 11 deletions(-)

diff --git a/drivers/net/axgbe/axgbe_dev.c b/drivers/net/axgbe/axgbe_dev.c index 3389954aa6..9b0073eea6 100644
--- a/drivers/net/axgbe/axgbe_dev.c
+++ b/drivers/net/axgbe/axgbe_dev.c
@@ -647,23 +647,21 @@ static void axgbe_config_dma_cache(struct axgbe_port *pdata)
        unsigned int arcache, awcache, arwcache;

        arcache = 0;
-       AXGMAC_SET_BITS(arcache, DMA_AXIARCR, DRC, 0x3);
+       AXGMAC_SET_BITS(arcache, DMA_AXIARCR, DRC, 0xf);
+       AXGMAC_SET_BITS(arcache, DMA_AXIARCR, TEC, 0xf);
+       AXGMAC_SET_BITS(arcache, DMA_AXIARCR, THC, 0xf);
        AXGMAC_IOWRITE(pdata, DMA_AXIARCR, arcache);

        awcache = 0;
-       AXGMAC_SET_BITS(awcache, DMA_AXIAWCR, DWC, 0x3);
-       AXGMAC_SET_BITS(awcache, DMA_AXIAWCR, RPC, 0x3);
-       AXGMAC_SET_BITS(awcache, DMA_AXIAWCR, RPD, 0x1);
-       AXGMAC_SET_BITS(awcache, DMA_AXIAWCR, RHC, 0x3);
-       AXGMAC_SET_BITS(awcache, DMA_AXIAWCR, RHD, 0x1);
-       AXGMAC_SET_BITS(awcache, DMA_AXIAWCR, RDC, 0x3);
-       AXGMAC_SET_BITS(awcache, DMA_AXIAWCR, RDD, 0x1);
+       AXGMAC_SET_BITS(awcache, DMA_AXIAWCR, DWC, 0xf);
+       AXGMAC_SET_BITS(awcache, DMA_AXIAWCR, RPC, 0xf);
+       AXGMAC_SET_BITS(awcache, DMA_AXIAWCR, RHC, 0xf);
+       AXGMAC_SET_BITS(awcache, DMA_AXIAWCR, RDC, 0xf);
        AXGMAC_IOWRITE(pdata, DMA_AXIAWCR, awcache);

        arwcache = 0;
-       AXGMAC_SET_BITS(arwcache, DMA_AXIAWRCR, TDWD, 0x1);
-       AXGMAC_SET_BITS(arwcache, DMA_AXIAWRCR, TDWC, 0x3);
-       AXGMAC_SET_BITS(arwcache, DMA_AXIAWRCR, RDRC, 0x3);
+       AXGMAC_SET_BITS(arwcache, DMA_AXIAWRCR, TDWC, 0xf);
+       AXGMAC_SET_BITS(arwcache, DMA_AXIAWRCR, RDRC, 0xf);
        AXGMAC_IOWRITE(pdata, DMA_AXIAWRCR, arwcache);  }

--
2.34.1