[PATCH] net/txgbe: fix a mass of interrupts
Ferruh Yigit
ferruh.yigit at amd.com
Mon Nov 18 20:59:17 CET 2024
On 11/15/2024 8:33 AM, Jiawen Wu wrote:
> Since firmware version 0x20010, GPIO interrupt enable is set to 0xd by
> default, which means enable bit 0 'tx_fault'. And GPIO interrupt polarity
> is set to 0xd by default too, which means these interrupts are rising-edge
> sensitive.
>
> So when unplug the SFP module, GPIO line 0 'tx_fault' is 0 -> 1 triggers
> the interrupt. However, the interrupt is not cleared. And GPIO interrupt
> mask is enabled and disabled to trigger the MISC interrupt repeatedly.
>
> Since this 'tx_fault' interrupt does not make much sense, simply clear it
> to fix the issue.
>
> Signed-off-by: Jiawen Wu <jiawenwu at trustnetic.com>
>
Hi Jiawen,
Can you please provide a fixes tag?
Also I believe you would like to backport this fix, if so please add the
stable tag as well.
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