[PATCH] net/mlx5: fix RSS hash for non-RSS CQE zipping

[Alexander Kozyrev]

Take the RSS hash value for the title packet for
flow tag and packet header CQE zipping formats.

Fixes: 54c2d46b16 ("net/mlx5: support flow tag and packet header miniCQEs")
Cc: stable at dpdk.org

Signed-off-by: Alexander Kozyrev <akozyrev at nvidia.com>
---
 drivers/net/mlx5/mlx5_rxtx_vec_altivec.h | 9 +++++----
 drivers/net/mlx5/mlx5_rxtx_vec_neon.h    | 9 +++++----
 drivers/net/mlx5/mlx5_rxtx_vec_sse.h     | 9 +++++----
 3 files changed, 15 insertions(+), 12 deletions(-)

diff --git a/drivers/net/mlx5/mlx5_rxtx_vec_altivec.h b/drivers/net/mlx5/mlx5_rxtx_vec_altivec.h
index 240987d03d..18452cc047 100644
--- a/drivers/net/mlx5/mlx5_rxtx_vec_altivec.h
+++ b/drivers/net/mlx5/mlx5_rxtx_vec_altivec.h
@@ -452,6 +452,7 @@ rxq_cq_decompress_v(struct mlx5_rxq_data *rxq, volatile struct mlx5_cqe *cq,
 				(uint32_t)t_pkt->ol_flags,
 				(uint32_t)t_pkt->ol_flags,
 				(uint32_t)t_pkt->ol_flags};
+			const uint32_t hash_rss = t_pkt->hash.rss;
 
 			ol_flags_mask = (__vector unsigned char)
 				vec_or((__vector unsigned long)ol_flags_mask,
@@ -470,10 +471,10 @@ rxq_cq_decompress_v(struct mlx5_rxq_data *rxq, volatile struct mlx5_cqe *cq,
 				((__vector unsigned int)ol_flags)[2];
 			elts[pos + 3]->ol_flags =
 				((__vector unsigned int)ol_flags)[3];
-			elts[pos]->hash.rss = 0;
-			elts[pos + 1]->hash.rss = 0;
-			elts[pos + 2]->hash.rss = 0;
-			elts[pos + 3]->hash.rss = 0;
+			elts[pos]->hash.rss = hash_rss;
+			elts[pos + 1]->hash.rss = hash_rss;
+			elts[pos + 2]->hash.rss = hash_rss;
+			elts[pos + 3]->hash.rss = hash_rss;
 		}
 		if (rxq->dynf_meta) {
 			int32_t offs = rxq->flow_meta_offset;
diff --git a/drivers/net/mlx5/mlx5_rxtx_vec_neon.h b/drivers/net/mlx5/mlx5_rxtx_vec_neon.h
index dc1d30753d..653a10867d 100644
--- a/drivers/net/mlx5/mlx5_rxtx_vec_neon.h
+++ b/drivers/net/mlx5/mlx5_rxtx_vec_neon.h
@@ -330,6 +330,7 @@ rxq_cq_decompress_v(struct mlx5_rxq_data *rxq, volatile struct mlx5_cqe *cq,
 				vdupq_n_u32(RTE_MBUF_F_RX_RSS_HASH);
 			const uint32x4_t rearm_flags =
 				vdupq_n_u32((uint32_t)t_pkt->ol_flags);
+			const uint32_t hash_rss = t_pkt->hash.rss;
 
 			ol_flags_mask = vorrq_u32(ol_flags_mask, hash_flags);
 			ol_flags = vorrq_u32(ol_flags,
@@ -338,10 +339,10 @@ rxq_cq_decompress_v(struct mlx5_rxq_data *rxq, volatile struct mlx5_cqe *cq,
 			elts[pos + 1]->ol_flags = vgetq_lane_u32(ol_flags, 2);
 			elts[pos + 2]->ol_flags = vgetq_lane_u32(ol_flags, 1);
 			elts[pos + 3]->ol_flags = vgetq_lane_u32(ol_flags, 0);
-			elts[pos]->hash.rss = 0;
-			elts[pos + 1]->hash.rss = 0;
-			elts[pos + 2]->hash.rss = 0;
-			elts[pos + 3]->hash.rss = 0;
+			elts[pos]->hash.rss = hash_rss;
+			elts[pos + 1]->hash.rss = hash_rss;
+			elts[pos + 2]->hash.rss = hash_rss;
+			elts[pos + 3]->hash.rss = hash_rss;
 		}
 		if (rxq->dynf_meta) {
 			int32_t offs = rxq->flow_meta_offset;
diff --git a/drivers/net/mlx5/mlx5_rxtx_vec_sse.h b/drivers/net/mlx5/mlx5_rxtx_vec_sse.h
index 81a177fce7..fd47677db1 100644
--- a/drivers/net/mlx5/mlx5_rxtx_vec_sse.h
+++ b/drivers/net/mlx5/mlx5_rxtx_vec_sse.h
@@ -314,6 +314,7 @@ rxq_cq_decompress_v(struct mlx5_rxq_data *rxq, volatile struct mlx5_cqe *cq,
 				_mm_set1_epi32(RTE_MBUF_F_RX_RSS_HASH);
 			const __m128i rearm_flags =
 				_mm_set1_epi32((uint32_t)t_pkt->ol_flags);
+			const uint32_t hash_rss = t_pkt->hash.rss;
 
 			ol_flags_mask = _mm_or_si128(ol_flags_mask, hash_flags);
 			ol_flags = _mm_or_si128(ol_flags,
@@ -326,10 +327,10 @@ rxq_cq_decompress_v(struct mlx5_rxq_data *rxq, volatile struct mlx5_cqe *cq,
 				_mm_extract_epi32(ol_flags, 2);
 			elts[pos + 3]->ol_flags =
 				_mm_extract_epi32(ol_flags, 3);
-			elts[pos]->hash.rss = 0;
-			elts[pos + 1]->hash.rss = 0;
-			elts[pos + 2]->hash.rss = 0;
-			elts[pos + 3]->hash.rss = 0;
+			elts[pos]->hash.rss = hash_rss;
+			elts[pos + 1]->hash.rss = hash_rss;
+			elts[pos + 2]->hash.rss = hash_rss;
+			elts[pos + 3]->hash.rss = hash_rss;
 		}
 		if (rxq->dynf_meta) {
 			int32_t offs = rxq->flow_meta_offset;
-- 
2.43.5