[PATCH v1 1/2] doc: clarify CB vs TB level device support

[Nicolas Chautru]

Clarify the support for different bbdev devices with regards
to code block vs transport block level processing which was
not explicit enough.

Signed-off-by: Nicolas Chautru <nicolas.chautru at intel.com>
---
 doc/guides/bbdevs/acc100.rst        | 1 +
 doc/guides/bbdevs/fpga_5gnr_fec.rst | 1 +
 doc/guides/bbdevs/fpga_lte_fec.rst  | 1 +
 doc/guides/bbdevs/vrb1.rst          | 1 +
 doc/guides/bbdevs/vrb2.rst          | 2 ++
 5 files changed, 6 insertions(+)

diff --git a/doc/guides/bbdevs/acc100.rst b/doc/guides/bbdevs/acc100.rst
index 6843e38c55..1621cc782f 100644
--- a/doc/guides/bbdevs/acc100.rst
+++ b/doc/guides/bbdevs/acc100.rst
@@ -17,6 +17,7 @@ ACC100 5G/4G FEC PMDs support the following features:
 - LDPC Decode in the UL (5GNR)
 - Turbo Encode in the DL (4G)
 - Turbo Decode in the UL (4G)
+- Support for code block level processing
 - 16 VFs per PF (physical device)
 - Maximum of 128 queues per VF
 - PCIe Gen-3 x16 Interface
diff --git a/doc/guides/bbdevs/fpga_5gnr_fec.rst b/doc/guides/bbdevs/fpga_5gnr_fec.rst
index 58d19ffbd2..b181527c45 100644
--- a/doc/guides/bbdevs/fpga_5gnr_fec.rst
+++ b/doc/guides/bbdevs/fpga_5gnr_fec.rst
@@ -16,6 +16,7 @@ FPGA 5GNR FEC PMD supports the following BBDEV capabilities:
 
 - LDPC Encode in the DL
 - LDPC Decode in the UL
+- Support for code block level processing
 - 8 VFs per PF (physical device)
 - Maximum of 32 UL queues per VF
 - Maximum of 32 DL queues per VF
diff --git a/doc/guides/bbdevs/fpga_lte_fec.rst b/doc/guides/bbdevs/fpga_lte_fec.rst
index 7e3748222c..990eeb087b 100644
--- a/doc/guides/bbdevs/fpga_lte_fec.rst
+++ b/doc/guides/bbdevs/fpga_lte_fec.rst
@@ -15,6 +15,7 @@ FPGA LTE FEC PMD supports the following features:
 
 - Turbo Encode in the DL with total throughput of 4.5 Gbits/s
 - Turbo Decode in the UL with total throughput of 1.5 Gbits/s assuming 8 decoder iterations
+- Support for code block level processing
 - 8 VFs per PF (physical device)
 - Maximum of 32 UL queues per VF
 - Maximum of 32 DL queues per VF
diff --git a/doc/guides/bbdevs/vrb1.rst b/doc/guides/bbdevs/vrb1.rst
index 255c4ea040..134dc246e7 100644
--- a/doc/guides/bbdevs/vrb1.rst
+++ b/doc/guides/bbdevs/vrb1.rst
@@ -30,6 +30,7 @@ These hardware blocks provide the following features exposed by the PMD:
 - LDPC Decode in the Uplink (5GNR)
 - Turbo Encode in the Downlink (4G)
 - Turbo Decode in the Uplink (4G)
+- Support for code block level processing
 - FFT processing
 - Single Root I/O Virtualization (SR-IOV) with 16 Virtual Functions (VFs) per Physical Function (PF)
 - Maximum of 256 queues per VF
diff --git a/doc/guides/bbdevs/vrb2.rst b/doc/guides/bbdevs/vrb2.rst
index 45c83e875f..ad67cc36a4 100644
--- a/doc/guides/bbdevs/vrb2.rst
+++ b/doc/guides/bbdevs/vrb2.rst
@@ -29,6 +29,8 @@ These hardware blocks provide the following features exposed by the PMD:
 - LDPC Decode in the Uplink (5GNR)
 - Turbo Encode in the Downlink (4G)
 - Turbo Decode in the Uplink (4G)
+- Support for code block level processing
+- Support for TB level processing for the LDPC Encode processing including CB concatenation.
 - FFT processing
 - MLD-TS processing
 - Single Root I/O Virtualization (SR-IOV) with 16 Virtual Functions (VFs) per Physical Function (PF)
-- 
2.34.1