[PATCH v1] doc/guides: update monitor PMD mode description

[Chris MacNamara]

A recent CPU change requires an extra enabling step for
the umonitor instruction on Intel CPUs.
This is now detailed in the l3 fwd power manager doc.

Signed-off-by: Chris MacNamara <chris.macnamara at intel.com>
---
 .mailmap                                          | 1 +
 doc/guides/sample_app_ug/l3_forward_power_man.rst | 5 +++++
 2 files changed, 6 insertions(+)

diff --git a/.mailmap b/.mailmap
index a03d3cfb59..c4bc38752f 100644
--- a/.mailmap
+++ b/.mailmap
@@ -263,6 +263,7 @@ Christopher Reder <christopher.reder at broadcom.com>
 Christoph Gysin <christoph.gysin at gmail.com>
 Christos Ricudis <ricudis at niometrics.com>
 Chris Wright <chrisw at redhat.com>
+Chris MacNamara <chris.macnamara at intel.com>
 Chuanshe Zhang <zhangchuanshe at icloudshield.com>
 Chuanyu Xue <chuanyu.xue at uconn.edu>
 Chuhong Yao <ych at panath.cn>
diff --git a/doc/guides/sample_app_ug/l3_forward_power_man.rst b/doc/guides/sample_app_ug/l3_forward_power_man.rst
index 3271bc2154..d0af28e0ec 100644
--- a/doc/guides/sample_app_ug/l3_forward_power_man.rst
+++ b/doc/guides/sample_app_ug/l3_forward_power_man.rst
@@ -293,6 +293,11 @@ and has three available power management schemes:
 ``monitor``
   This will use ``rte_power_monitor()`` function to enter
   a power-optimized state (subject to platform support).
+  On recent Gen 4 Xeon Scalable Processors the umonitor instruction
+  is disabled by default.
+  An additional step is required to enable the umonitor instruction.
+  Writing 0 to bit 6 of register 0x123 will enable umonitor.
+  `More details are available via Monitor and Umonitor Performance Guidance <https://www.intel.com/content/www/us/en/developer/articles/technical/software-security-guidance/technical-documentation/monitor-umonitor-performance-guidance.html>`_
 
 ``pause``
   This will use ``rte_power_pause()`` or ``rte_pause()``
-- 
2.43.0

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