[PATCH] config/riscv: add rv64gcv cross compilation target

[sunyuechi at iscas.ac.cn]

Hi, how is this patch?


> -----原始邮件-----
> 发件人: sunyuechi at iscas.ac.cn
> 发送时间: 2025-09-23 23:07:34 (星期二)
> 收件人: dev at dpdk.org
> 抄送: "Sun Yuechi" <sunyuechi at iscas.ac.cn>, "Stanisław Kardach" <stanislaw.kardach at gmail.com>, "Bruce Richardson" <bruce.richardson at intel.com>
> 主题: [PATCH] config/riscv: add rv64gcv cross compilation target
> 
> From: Sun Yuechi <sunyuechi at iscas.ac.cn>
> 
> Add a cross file for rv64gcv, enable it in devtools/test-meson-builds.sh,
> and update the RISC-V cross-build guide to support the vector extension.
> 
> Signed-off-by: Sun Yuechi <sunyuechi at iscas.ac.cn>
> ---
>  config/riscv/meson.build                        |  3 ++-
>  config/riscv/riscv64_rv64gcv_linux_gcc          | 17 +++++++++++++++++
>  devtools/test-meson-builds.sh                   |  4 ++++
>  .../linux_gsg/cross_build_dpdk_for_riscv.rst    |  2 ++
>  4 files changed, 25 insertions(+), 1 deletion(-)
>  create mode 100644 config/riscv/riscv64_rv64gcv_linux_gcc
> 
> diff --git a/config/riscv/meson.build b/config/riscv/meson.build
> index f3daea0c0e..a06429a1e2 100644
> --- a/config/riscv/meson.build
> +++ b/config/riscv/meson.build
> @@ -43,7 +43,8 @@ vendor_generic = {
>          ['RTE_MAX_NUMA_NODES', 2]
>      ],
>      'arch_config': {
> -        'generic': {'machine_args': ['-march=rv64gc']}
> +        'generic': {'machine_args': ['-march=rv64gc']},
> +        'rv64gcv': {'machine_args': ['-march=rv64gcv']},
>      }
>  }
>  
> diff --git a/config/riscv/riscv64_rv64gcv_linux_gcc b/config/riscv/riscv64_rv64gcv_linux_gcc
> new file mode 100644
> index 0000000000..ccc5115dec
> --- /dev/null
> +++ b/config/riscv/riscv64_rv64gcv_linux_gcc
> @@ -0,0 +1,17 @@
> +[binaries]
> +c = ['ccache', 'riscv64-linux-gnu-gcc']
> +cpp = ['ccache', 'riscv64-linux-gnu-g++']
> +ar = 'riscv64-linux-gnu-ar'
> +strip = 'riscv64-linux-gnu-strip'
> +pcap-config = ''
> +
> +[host_machine]
> +system = 'linux'
> +cpu_family = 'riscv64'
> +cpu = 'rv64gcv'
> +endian = 'little'
> +
> +[properties]
> +vendor_id = 'generic'
> +arch_id = 'rv64gcv'
> +pkg_config_libdir = '/usr/lib/riscv64-linux-gnu/pkgconfig'
> diff --git a/devtools/test-meson-builds.sh b/devtools/test-meson-builds.sh
> index 4fff1f7177..4f07f84eb0 100755
> --- a/devtools/test-meson-builds.sh
> +++ b/devtools/test-meson-builds.sh
> @@ -290,6 +290,10 @@ build build-ppc64-power8-gcc $f ABI $use_shared
>  f=$srcdir/config/riscv/riscv64_linux_gcc
>  build build-riscv64-generic-gcc $f ABI $use_shared
>  
> +# RISC-V vector (rv64gcv)
> +f=$srcdir/config/riscv/riscv64_rv64gcv_linux_gcc
> +build build-riscv64_rv64gcv_gcc $f ABI $use_shared
> +
>  # Test installation of the x86-generic target, to be used for checking
>  # the sample apps build using the pkg-config file for cflags and libs
>  load_env cc
> diff --git a/doc/guides/linux_gsg/cross_build_dpdk_for_riscv.rst b/doc/guides/linux_gsg/cross_build_dpdk_for_riscv.rst
> index 7d7f7ac72b..bcba12a604 100644
> --- a/doc/guides/linux_gsg/cross_build_dpdk_for_riscv.rst
> +++ b/doc/guides/linux_gsg/cross_build_dpdk_for_riscv.rst
> @@ -108,6 +108,8 @@ Currently the following targets are supported:
>  
>  * Generic rv64gc ISA: ``config/riscv/riscv64_linux_gcc``
>  
> +* RV64GCV ISA: ``config/riscv/riscv64_rv64gcv_linux_gcc``
> +
>  * SiFive U740 SoC: ``config/riscv/riscv64_sifive_u740_linux_gcc``
>  
>  To add a new target support, ``config/riscv/meson.build`` has to be modified by
> -- 
> 2.51.0
</sunyuechi at iscas.ac.cn></sunyuechi at iscas.ac.cn></bruce.richardson at intel.com></stanislaw.kardach at gmail.com></sunyuechi at iscas.ac.cn>