[PATCH v7 04/47] net/sxe2: fix MSIX register width in PF map table

[liujie5 at linkdatatechnology.com]

From: Jie Liu <liujie5 at linkdatatechnology.com>

The MSIX entry in sxe2_net_map_addr_info_pf sets a register width
of 10 (decimal), but each PCIe MSIX table entry is 16 bytes (0x10).
The VF map table already uses 0x10.

Since reg_width is used as the stride between MSIX entries in
sxe2_dev_pci_seg_map(), the wrong value makes the mapped region too
short and places the entries at incorrect offsets.

Change .reg_width from 10 to 0x10 for the SXE2_PCI_MAP_RES_IRQ_MSIX
entry to match the VF table.

Fixes: 66a10eb60ebe ("net/sxe2: add PCI BAR mapping")
Cc: stable at dpdk.org
Cc: stephen at networkplumber.org
Signed-off-by: Jie Liu <liujie5 at linkdatatechnology.com>
---
 drivers/net/sxe2/sxe2_ethdev.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/net/sxe2/sxe2_ethdev.c b/drivers/net/sxe2/sxe2_ethdev.c
index ec376b76dc..5d8cfca6cf 100644
--- a/drivers/net/sxe2/sxe2_ethdev.c
+++ b/drivers/net/sxe2/sxe2_ethdev.c
@@ -94,7 +94,7 @@ static struct sxe2_pci_map_addr_info sxe2_net_map_addr_info_pf[SXE2_PCI_MAP_RES_
 				      .reg_width = 4},
 	[SXE2_PCI_MAP_RES_IRQ_MSIX] = {.addr_base = SXE2_BAR4_MSIX_CTL(0),
 				      .bar_idx = 4,
-				      .reg_width = 10},
+				      .reg_width = 0x10},
 };
 
 static struct sxe2_pci_map_addr_info sxe2_net_map_addr_info_vf[SXE2_PCI_MAP_RES_MAX_COUNT] = {
-- 
2.52.0