[PATCH v3 1/6] net/iavf: increase max ring descriptors to hardware limit

[Bruce Richardson]

On Tue, Jun 30, 2026 at 08:06:51AM -0400, Dawid Wesierski wrote:
> From: Marek Kasiewicz <marek.kasiewicz at intel.com>
> 
> The Intel E810 hardware supports up to 8160 (8K - 32) descriptors per
> TX/RX ring, but IAVF_MAX_RING_DESC caps it at 4096. Applications that
> need deep descriptor rings for hardware rate-limited pacing (e.g.,
> ST2110 video with thousands of packets per frame) cannot queue enough
> packets before the pacing epoch begins.
> 
> Increase IAVF_MAX_RING_DESC to the hardware maximum of 8160 to allow
> full utilization of the ring depth on E810 VFs.
> 
> Signed-off-by: Marek Kasiewicz <marek.kasiewicz at intel.com>
> Signed-off-by: Dawid Wesierski <dawid.wesierski at intel.com>

Acked-by: Bruce Richardson <bruce.richardson at intel.com>

> ---
>  .mailmap                           | 2 ++
>  drivers/net/intel/iavf/iavf_rxtx.h | 2 +-
>  2 files changed, 3 insertions(+), 1 deletion(-)
> 
> diff --git a/.mailmap b/.mailmap
> index 4001e5fb0e..d7b175de2a 100644
> --- a/.mailmap
> +++ b/.mailmap
> @@ -366,6 +366,7 @@ David Zeng <zengxhsh at cn.ibm.com>
>  Davide Caratti <dcaratti at redhat.com>
>  Dawid Gorecki <dgr at semihalf.com>
>  Dawid Jurczak <dawid_jurek at vp.pl>
> +Dawid Wesierski <dawid.wesierski at intel.com>
>  Dawid Zielinski <dawid.zielinski at intel.com>
>  Dawid Łukwiński <dawid.lukwinski at intel.com>
>  Daxue Gao <daxuex.gao at intel.com>
> @@ -1014,6 +1015,7 @@ Marcin Wilk <marcin.wilk at caviumnetworks.com>
>  Marcin Wojtas <mw at semihalf.com>
>  Marcin Zapolski <marcinx.a.zapolski at intel.com>
>  Marco Varlese <mvarlese at suse.de>
> +Marek Kasiewicz <marek.kasiewicz at intel.com>
>  Marek Mical <marekx.mical at intel.com>
>  Marek Zalfresso-jundzillo <marekx.zalfresso-jundzillo at intel.com>
>  Maria Lingemark <maria.lingemark at ericsson.com>
> diff --git a/drivers/net/intel/iavf/iavf_rxtx.h b/drivers/net/intel/iavf/iavf_rxtx.h
> index 8449236d4d..22ea415f44 100644
> --- a/drivers/net/intel/iavf/iavf_rxtx.h
> +++ b/drivers/net/intel/iavf/iavf_rxtx.h
> @@ -16,7 +16,7 @@
>  /* In QLEN must be whole number of 32 descriptors. */
>  #define IAVF_ALIGN_RING_DESC      32
>  #define IAVF_MIN_RING_DESC        64
> -#define IAVF_MAX_RING_DESC        4096
> +#define IAVF_MAX_RING_DESC        (8192 - 32)
>  #define IAVF_DMA_MEM_ALIGN        4096
>  /* Base address of the HW descriptor ring should be 128B aligned. */
>  #define IAVF_RING_BASE_ALIGN      128
> -- 
> 2.47.3
> 
> ---------------------------------------------------------------------
> Intel Technology Poland sp. z o.o.
> ul. Slowackiego 173 | 80-298 Gdansk | Sad Rejonowy Gdansk Polnoc | VII Wydzial Gospodarczy Krajowego Rejestru Sadowego - KRS 101882 | NIP 957-07-52-316 | Kapital zakladowy 200.000 PLN.
> Spolka oswiadcza, ze posiada status duzego przedsiebiorcy w rozumieniu ustawy z dnia 8 marca 2013 r. o przeciwdzialaniu nadmiernym opoznieniom w transakcjach handlowych.
> 
> Ta wiadomosc wraz z zalacznikami jest przeznaczona dla okreslonego adresata i moze zawierac informacje poufne. W razie przypadkowego otrzymania tej wiadomosci, prosimy o powiadomienie nadawcy oraz trwale jej usuniecie; jakiekolwiek przegladanie lub rozpowszechnianie jest zabronione.
> This e-mail and any attachments may contain confidential material for the sole use of the intended recipient(s). If you are not the intended recipient, please contact the sender and delete all copies; any review or distribution by others is strictly prohibited.