[PATCH v4 0/2] RISC-V vector extension support

[Sun Yuechi]

v4:
- Removed duplicate macro definitions of RTE_LPM_LOOKUP_SUCCESS and
  RTE_LPM_VALID_EXT_ENTRY_BITMASK
- Split SIMD bitwidth change into separate patch

Sun Yuechi (2):
  eal/riscv: set default SIMD bitwidth to 128
  node: lookup with RISC-V vector extension

 doc/guides/rel_notes/release_26_03.rst |   4 +
 lib/eal/riscv/include/rte_vect.h       |   2 +-
 lib/node/ip4_lookup.c                  |   5 +-
 lib/node/ip4_lookup_rvv.h              | 164 +++++++++++++++++++++++++
 4 files changed, 173 insertions(+), 2 deletions(-)
 create mode 100644 lib/node/ip4_lookup_rvv.h

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2.53.0