[PATCH v3] acl: add RISC-V vector extension implementation

[sunyuechi]

On 2/2/26 12:09 AM, Sun Yuechi wrote:

> Implement ACL classify function for RISC-V architecture
> using RISC-V Vector Extension instruction set.
>
> Signed-off-by: Sun Yuechi <sunyuechi at iscas.ac.cn>
> Signed-off-by: Zijian <zijian.oerv at isrc.iscas.ac.cn>
> Acked-by: Konstantin Ananyev <konstantin.ananyev at huawei.com>
> ---
>   app/test-acl/main.c                    |   4 +
>   app/test/test_acl.c                    |   1 +
>   config/riscv/meson.build               |   1 +
>   doc/guides/rel_notes/release_26_03.rst |   6 +
>   examples/l3fwd/l3fwd_acl.c             |   4 +
>   lib/acl/acl.h                          |   4 +
>   lib/acl/acl_run.h                      |   2 +
>   lib/acl/acl_run_rvv.c                  |  18 ++
>   lib/acl/acl_run_rvv.h                  | 326 +++++++++++++++++++++++++
>   lib/acl/meson.build                    |   2 +
>   lib/acl/rte_acl.c                      |  34 +++
>   lib/acl/rte_acl.h                      |   1 +
>   lib/eal/riscv/include/rte_vect.h       |   2 +-
>   13 files changed, 404 insertions(+), 1 deletion(-)
>   create mode 100644 lib/acl/acl_run_rvv.c
>   create mode 100644 lib/acl/acl_run_rvv.h
ping